ADV7183ABST datasheet(18/104 Pages) AD

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ADV7183A

Rev. A | Page 18 of 104

Drive Strength Selection (Clock)

DR_STR_C[1:0] Address 0x0E, [3:2]

The DR_STR_C[1:0] bits can be used to select the strength of

the clock signal output driver (LLC pin). For more information,

refer to the following sections:

•

Drive Strength Selection (Sync)

•

Drive Strength Selection (Data)

Table 21. DR_STR Function

DR_STR[1:0]

Description

Low drive strength (1×).

01*

Medium low drive strength (2×).

Medium high drive strength (3×).

High drive strength (4×).

*Default value.

Drive Strength Selection (Sync)

DR_STR_S[1:0] Address 0x0E, [1:0]

The DR_STR_S[1:0] bits allow the user to select the strength of

the synchronization signals with which HS, VS, and F are

driven. For more information, refer to the following sections:

•

Drive Strength Selection (Clock)

•

Drive Strength Selection (Data)

Table 22. DR_STR Function

DR_STR[1:0]

Description

Low drive strength (1×).

01*

Medium low drive strength (2×).

Medium high drive strength (3×).

High drive strength (4×).

*Default value.

Enable Subcarrier Frequency Lock Pin

EN_SFL_PIN Address 0x04, [1]

The subcarrier frequency lock pin (SDP, output only) has a

double function: it can also output raw sync-related information

(SogOut). The EN_SFL_PIN bit enables the output of

subcarrier lock information (also known as GenLock) from the

SDP core to an encoder in a decoder-encoder back-to-back

arrangement.

Table 23. EN_SFL_PIN

EN_SFL_PIN

Description

Subcarrier frequency lock output is disabled.

Subcarrier frequency lock information is

presented on the SFL pin.

*Default value.

Polarity LLC Pin

PCLK Address 0x37, [0]

The polarity of the clock that leaves the ADV7183A via the

LLC1 and LLC2 pins can be inverted using the PCLK bit. Note

that this inversion affects the clock for SDP.

Changing the polarity of the LLC clock output may be

necessary to meet the setup-and-hold time expectations of

follow-on chips.

Note that this bit also inverts the polarity of the LLC2 clock.

Table 24. PCLK Function

PCLK

Description

Invert LLC output polarity.

LLC output polarity normal (as per the Timing

Diagrams)

*Default value.

ADV7183ABST Datasheet(PDF) 18 Page - Analog Devices

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