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ADV7183ABST Datasheet(PDF) 73 Page - Analog Devices |
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ADV7183ABST Datasheet(HTML) 73 Page - Analog Devices |
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73 / 104 page ![]() ADV7183A Rev. A | Page 73 of 104 Table 178. Register 0x04 Bit Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Comments 0 16 < Y < 235, 16 < C < 240 ITU-R BT.656 RANGE. Allows the user to select the range of output values. Can be BT656 compliant, or can fill the whole accessible number range. 1 1 < Y < 254, 1 < C < 254 Extended Range 0 SFL output is disabled EN_SFL_PIN 1 SFL information output on the SFL pin SFL output enables encoder and decoder to be connected directly. 0 Decode and output color BL_C_VBI. Blank Chroma during VBI. If set, enables data in the VBI region to be passed through the decoder undistorted. 1 Blank Cr and Cb During VBI 0 HS, VS, F three- stated TIM_OE. Timing signals output enable. 1 HS, VS, F forced active Controlled by TOD 0 0 Low drive, 1× 0 1 Medium-low, 2× 1 0 Medium-high, 3× DR_STR[1:0]. Drive strength of output drivers can be increased or decreased for EMC or crosstalk reasons. 1 1 High drive, 4× Recommended Reserved 1 Set to default 0 BT656-3 compatible 0x04 Extended Output Control BT656-4. Allows the user to select an output mode compatible with ITU- R BT656-3/4. 1 BT656-4 compatible |
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