ADV7183ABST datasheet(12/104 Pages) AD

12 / 104 page

ADV7183A

Rev. A | Page 12 of 104

Pin No.

Mnemonic

Type

Function

XTAL

This is the input pin for the 27 MHz crystal, or can be overdriven by an external 3.3 V,

27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.

XTAL1

This pin should be connected to the 27 MHz crystal or left as a no connect if an external

3.3 V, 27 MHz clock oscillator source is used to clock the ADV7183A. In crystal mode, the

crystal must be a fundamental crystal.

PWRDN

A logic low on this pin places the ADV7183A in a power-down mode. Refer to the I2C

Control Register Map for more options on power-down modes for the ADV7183A.

When set to a logic low, OE enables the pixel output bus, P15–P0 of the ADV7183A. A logic

high on the OE pin places Pins P15–P0, HS, VS, SFL/SYNC_OUT into a high impedance state.

ELPF

The recommended external loop filter must be connected to this ELPF pin, as shown in

Figure 42.

SFL

Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock

the subcarrier frequency when this decoder is connected to any Analog Devices, Inc. digital

video encoder.

REFOUT

Internal Voltage Reference Output. Refer to Figure 42 for a recommended capacitor

network for this pin.

CML

The CML pin is a common-mode level for the internal ADCs. Refer to Figure 42 for a

recommended capacitor network for this pin.

48, 49

CAPY1, CAPY2

ADC’s Capacitor Network. Refer to Figure 42 for a recommended capacitor network for

this pin.

54, 55

CAPC1, CAPC2

ADC’s Capacitor Network. Refer to Figure 42 for a recommended capacitor network for

this pin.

ADV7183ABST Datasheet(PDF) 12 Page - Analog Devices