ADV7183ABST datasheet(63/104 Pages) AD

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ADV7183A

Rev. A | Page 63 of 104

PIXEL PORT CONFIGURATION

The ADV7183A has a very flexible pixel port that can be

config-ured in a variety of formats to accommodate

downstream ICs. Table 168 and Table 169 summarize the

various functions that the ADV7183A’s pins can have in

different modes of operation.

The ordering of components (e.g., Cr versus Cb, CHA/B/C) can

be changed. Refer to the SWPC Swap Pixel Cr/Cb (SDP),

Address 0x27, [7] section. Table 168 indicates the default

positions for the Cr/Cb components.

OF_SEL[3:0] Output Format Selection, Address 0x03, [5:2]

There are several modes in which the ADV7183A pixel port can

be configured. These modes are under the control of

OF_SEL[3:0]. See Table 169 for details.

The default LLC frequency output on the LLC1 pin is approxi-

mately 27 MHz. For modes that operate with a nominal data

rate of 13.5 MHz (0001, 0010), the clock frequency on the LLC1

pin stays at the higher rate of 27 MHz. For information on

outputting the nominal 13.5 MHz clock on the LLC1 pin, see

the LLC1 Output Selection, LLC_PAD_SEL[2:0] (SDP),

Address 0x8F, [6:4] section.

SWPC Swap Pixel Cr/Cb (SDP), Address 0x27, [7]

This bit allows Cr and Cb samples of the SDP block to be

swapped.

Table 166. SWPC Function

SWPC

Description

No swapping.

Swap Cr and Cb values.

*Default value.

LLC1 Output Selection, LLC_PAD_SEL[2:0] (SDP),

Address 0x8F, [6:4]

The following I2C write allows the user to select between the

LLC1 (nominally at 27 MHz) and LLC2 (nominally at

13.5 MHz).

The LLC2 signal is useful for LLC2 compatible wide bus

(16-bit) output modes. See OF_SEL[3:0] Output Format

Selection, Address 0x03, [5:2] for additional information. The

LLC2 signal and data on the data bus are synchronized. By

default, the rising edge of LLC1/LLC2 is aligned with the Y data;

the falling edge occurs when the data bus holds C data. The

polarity of the clock, and therefore the Y/C assignments to the

clock edges, can be altered by using the Polarity LLC pin.

Table 167. LLC_PAD_SEL Function

LLC_PAD_SEL[2:0]

Description

000*

Output nominal 27 MHz LLC on LLC1 pin

101

Output nominal 13.5 MHz LLC on LLC1 pin

*Default value.

Table 168. P15–P0 Output/Input Pin Mapping

Data Port Pins P[15:0]

Processor, Format, and Mode

SDP

Video Out, 8-Bit, 4:2:2

YCrCb[7:0]OUT

SDP

Video Out, 16-Bit, 4:2:2

Y[7:0]OUT

CrCb[7:0] OUT

Table 169. Standard Definition Pixel Port Modes

P[15: 0]

OF_SEL[3:0]

Format

P[15:8]

P[7: 0]

0010

16-Bit @LLC2 4:2:2

Y[7:0]

CrCb[7:0]

0011*

8-Bit @LLC1 4:2:2

YCrCb[7:0]

Three-State

0110-1111

Reserved

Reserved. Do not use.

*Default value.

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