ADV7183ABST datasheet(24/104 Pages) AD

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ADV7183A

Rev. A | Page 24 of 104

Lock Related Controls (SDP)

Lock information is presented to the user through Bits [1:0] of

the Status 1 register. See the STATUS_1[7:0] Address 0x10, [7:0]

section. Figure 9 outlines the signal flow and the controls

available to influence the way the lock status information is

generated.

SRLS Select Raw Lock Signal (SDP), Address 0x51, [6]

Using the SRLS bit, the user can choose between two sources for

determining the lock status (per Bits [1:0] in the Status 1

•

The time_win signal is based on a line-to-line evaluation of

the horizontal synchronization pulse of the incoming

video. It reacts quite quickly.

•

The free_run signal evaluates the properties of the

incoming video over several fields, and takes vertical

synchronization information into account.

Table 40. SRLS Function

SRLS

Description

Select the free_run signal.

Select the time_win signal.

*Default value.

FSCLE Fsc Lock Enable (SDP), Address 0x51, [7]

The FSCLE bit allows the user to choose whether the status of

the color subcarrier loop is taken into account when the overall

lock status is determined and presented via Bits [1:0] in Status

YPrPb component mode in order to generate a reliable HLOCK

status bit.

Table 41. FSCLE Function

FSCLE

Description

Overall lock status only dependent on horizontal

sync lock.

Overall lock status dependent on horizontal sync

lock and Fsc Lock.

*Default value.

CIL[2:0] Count Into Lock (SDP), Address 0x51, [2:0]

CIL[2:0] determines the number of consecutive lines for which

the into lock condition must be true before the system switches

into the locked state, and reports this via Status 0 [1:0].

Table 42. CIL Function

CIL[2:0]

Description (Count Value in Lines of Video)

000

001

010

011

100*

100

101

500

110

1000

111

100000

*Default value.

COL[2:0] Count Out of Lock (SDP), Address 0x51, [5:3]

COL[2:0] determines the number of consecutive lines for which

the out of lock condition must be true before the system

switches into unlocked state, and reports this via Status 0 [1:0].

Table 43. COL Function

COL[2:0]

Description (Count Value in Lines of Video)

000

001

010

011

100*

100

101

500

110

1000

111

100000

*Default value.

TIME_WIN

FREE_RUN

STATUS 1 [0]

SELECT THE RAW LOCK SIGNAL

SRLS

FILTER THE RAW LOCK SIGNAL

CIL[2:0], COL[2:0]

TAKE FSC LOCK INTO ACCOUNT

FSCLE

STATUS 1 [1]

FSC LOCK

COUNTER INTO LOCK

COUNTER OUT OF LOCK

MEMORY

Figure 9. SDP Lock Related Signal Path

ADV7183ABST Datasheet(PDF) 24 Page - Analog Devices

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