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ADV7183ABST Datasheet(PDF) 14 Page - Analog Devices |
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ADV7183ABST Datasheet(HTML) 14 Page - Analog Devices |
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14 / 104 page  ADV7183A Rev. A | Page 14 of 104 SET INSEL[3:0] TO CONFIGURE ADV7183A TO DECODE VIDEO FORMAT: CVBS: 0000 YC: 0110 YPrPb: 1001 USE MANUAL INPUT MUXING (ADC_SW_MAN_EN, ADC0_SW, ADC1_SW, ADC2_SW) SET INSEL[3:0] FOR REQUIRED MUXING CONFIGURATION CONNECTING ANALOG SIGNALS TO ADV7183A ADI RECOMMENDED INPUT MUXING; SEE TABLE 9 YES NO Figure 7. Input Muxing Overview Table 8. Input Channel Switching Using INSEL[3:0] Description INSEL[3:0] Analog Input Pins Video Format (SDP) 0000* CVBS1 = AIN1 Composite 0001 CVBS2 = AIN2 Composite 0010 CVBS3 = AIN3 Composite 0011 CVBS4 = AIN4 Composite 0100 CVBS5 = AIN5 Composite 0101 CVBS6 = AIN6 Composite 0110 Y1 = AIN1 YC C1 = AIN4 YC 0111 Y2 = AIN2 YC C2 = AIN5 YC 1000 Y3 = AIN3 YC C3 = AIN6 YC 1001 Y1 = AIN1 YPrPb PR1 = AIN4 YPrPb PB1 = AIN5 YPrPb 1010 Y2 = AIN2 YPrPb PR2 = AIN3 YPrPb PB2 = AIN6 YPrPb 1011 CVBS7 = AIN7 Composite 1100 CVBS8 = AIN8 Composite 1101 CVBS9 = AIN9 Composite 1110 CVBS10 = AIN10 Composite 1111 CVBS11 = AIN11 Composite *Default value. Table 9. Input Channel Assignments Input Channel Pin No. ADI Recommended Input Muxing Control INSEL[3:0] AIN7 41 CVBS7 AIN1 42 CVBS1 YC1-Y YPrPb1-Y AIN8 43 CVBS8 AIN2 44 CVBS2 YC2-Y YPrPb2-Y AIN9 45 CVBS9 AIN3 46 CVBS3 YC3-Y YPrPb2-Pb AIN10 57 CVBS10 AIN4 58 CVBS4 YC1-C YPrPb1-Pb AIN11 59 CVBS11 AIN5 60 CVBS5 YC2-C YPrPb1-Pr AIN12 61 Not Available AIN6 62 CVBS6 YC3-C YPrPb2-Pr ADI recommended input muxing is designed to minimize crosstalk between signal channels and to obtain the highest level of signal integrity. Table 9 summarizes how PCB layout should connect analog video signals to the ADV7183A. Notes • It is strongly recommended to connect any unused analog input pins to AGND to act as a shield. • Inputs AIN7 to AIN11 should be connected to AGND in cases where only six input channels are used. This will improve the quality of the sampling due to better isolation between the channels. • AIN12 is not under the control of INSEL[3:0]. It can only be routed to ADC0/ADC1/ADC2 by manual muxing. See Table 10 for further details. |
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