LFEC datasheet(36/117 Pages) LATTICE

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Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Oscillator

Every LatticeECP/EC device has an internal CMOS oscillator which is used to derive a master serial clock for con-

ﬁguration. The oscillator and the master serial clock run continuously. The default value of the master serial clock is

2.5MHz. Table 2-15 lists all the available Master Serial Clock frequencies. When a different Master Serial Clock is

selected during the design process, the following sequence takes place:

User selects a different Master Serial Clock frequency.

During conﬁguration the device starts with the default (2.5MHz) Master Serial Clock frequency.

The clock conﬁguration settings are contained in the early conﬁguration bit stream.

The Master Serial Clock frequency changes to the selected frequency once the clock conﬁguration bits are

received.

For further information on the use of this oscillator for conﬁguration, please see details of additional technical docu-

mentation at the end of this data sheet.

Table 2-15. Selectable Master Serial Clock (CCLK) Frequencies During Conﬁguration

Density Shifting

The LatticeECP/EC family has been designed to ensure that different density devices in the same package have

the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration

from lower density parts to higher density parts. In many cases, it is also possible to shift a lower utilization design

targeted for a high-density device to a lower density device. However, the exact details of the ﬁnal resource utiliza-

tion will impact the likely success in each case.

CCLK (MHz)

2.5*

4.3

5.4

6.9

8.1

130

9.2

—

10.0

—

LFEC Datasheet(PDF) 36 Page - Lattice Semiconductor