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LFEC Datasheet(PDF) 59 Page - Lattice Semiconductor |
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LFEC Datasheet(HTML) 59 Page - Lattice Semiconductor |
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59 / 117 page  3-23 DC and Switching Characteristics Lattice Semiconductor LatticeECP/EC Family Data Sheet LatticeECP/EC sysCONFIG Port Timing Specifications Over Recommended Operating Conditions Parameter Description Min Max Units sysCONFIG Byte Data Flow tSUCBDI Byte D[0:7] Setup Time to CCLK 7 — ns tHCBDI Byte D[0:7] Hold Time to CCLK 1 — ns tCODO Clock to Dout in Flowthrough Mode — TBD ns tSUCS CS[0:1] Setup Time to CCLK 7 — ns tHCS CS[0:1] Hold Time to CCLK 1 — ns tSUWD Write Signal Setup Time to CCLK 7 — ns tHWD Write Signal Hold Time to CCLK 1 — ns tDCB CCLK to BUSY Delay Time — 12 ns tCORD Clock to out for read Data — 12 ns sysCONFIG Byte Slave Clocking tBSCH Byte Slave Clock Minimum High Pulse 6 — ns tBSCL Byte Slave Clock Minimum Low Pulse 6 — ns tBSCYC Byte Slave Clock Cycle Time 15 — ns sysCONFIG Serial (Bit) Data Flow tSUSCDI Din Setup Time to CCLK Slave Mode 7 — ns tHSCDI Din Hold Time to CCLK Slave Mode 1 — ns tCODO Clock to Dout in Flowthrough Mode — 12 ns tSUMCDI Din Setup Time to CCLK Master Mode 7 — ns tHMCDI Din Hold Time to CCLK Master Mode 1 — ns sysCONFIG Serial Slave Clocking tSSCH Serial Slave Clock Minimum High Pulse 6 — ns tSSCL Serial Slave Clock Minimum Low Pulse 6 — ns sysCONFIG POR, Initialization and Wake Up tICFG Minimum Vcc to INIT High — 50 ms tVMC Time from tICFG to valid Master Clock — 2 us tPRGMRJ PROGRAMB Pin Pulse Rejection — 10 ns tPRGM PROGRAMB Low Time to Start Configuration 25 — ns tDINIT PROGRAMB High to INIT High Delay — 1 ms tDPPINIT Delay Time from PROGRAMB Low to INIT Low — 37 ns tDPPDONE Delay Time from PROGRAMB Low to DONE Low — 37 ns tIODISS User I/O Disable from PROGRAMB Low — 25 ns tIOENSS User I/O Enabled Time from CCLK Edge During Wake-up Sequence — 25 ns tMWC Additional Wake Master Clock Signals after Done Pin High 120 — cycles sysCONFIG SPI Port tCFGX Init High to CCLK Low — 1 µs tCSSPI Init High to CSSPIN Low — 2 us tCSCCLK CCLK Low before CSSPIN Low 0 - ns tSOCDO CCLK Low to Output Valid — 15 ns tSOE CSSPIN Active Setup Time 300 — ns tCSPID CSSPIN Low to First Clock Edge Setup Time 300+3cyc 600+6cyc ns fMAXSPI Max Frequency for SPI — 20 MHz |
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