Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

LFEC Datasheet(PDF) 52 Page - Lattice Semiconductor

Part # LFEC
Description  LatticeECP/EC Family Data Sheet
PDF  117 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LFEC Datasheet(HTML) 52 Page - Lattice Semiconductor

Back Button LFEC Datasheet HTML 48Page - Lattice Semiconductor LFEC Datasheet HTML 49Page - Lattice Semiconductor LFEC Datasheet HTML 50Page - Lattice Semiconductor LFEC Datasheet HTML 51Page - Lattice Semiconductor LFEC Datasheet HTML 52Page - Lattice Semiconductor LFEC Datasheet HTML 53Page - Lattice Semiconductor LFEC Datasheet HTML 54Page - Lattice Semiconductor LFEC Datasheet HTML 55Page - Lattice Semiconductor LFEC Datasheet HTML 56Page - Lattice Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 52 / 117 page
background image
3-16
DC and Switching Characteristics
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
tHWREN_EBR
Hold Write/Read Enable to PFU Memory
0.23
-
0.28
-
0.33
-
ns
tSUCE_EBR
Clock Enable Setup Time to EBR Output
Register
0.28
-
0.34
-
0.40
-
ns
tHCE_EBR
Clock Enable Hold Time to EBR Output
Register
-0.24
-
-0.29
-
-0.34
-
ns
tRSTO_EBR
Reset To Output Delay Time from EBR Out-
put Register
-
1.00
-
1.20
-
1.40
ns
PLL Parameters
tRSTREC
Reset Recovery to Rising Clock
-
-
-
ns
tRSTSU
Reset Signal Setup Time
-
-
-
ns
tRSTW
Reset Signal Pulse Width
10.0
-
10.0
-
10.0
-
ns
DSP Block Timing
2
tSUI_DSP
Input Register Setup Time
-
-0.44
-
-0.35
-
-0.27
ns
tHI_DSP
Input Register Hold Time
-
0.80
-
0.96
-
1.12
ns
tSUP_DSP
Pipeline Register Setup Time
-
3.31
-
3.98
-
4.64
ns
tHP_DSP
Pipeline Register Hold Time
-
0.80
-
0.96
-
1.12
ns
tSUO_DSP
Output Register Setup Time
-
6.72
-
8.07
-
9.41
ns
tHO_DSP
Output Register Hold Time
-
0.80
-
0.96
-
1.12
ns
tCOI_DSP
Input Register Clock to Output Time
-
8.33
-
10.35
-
12.07
ns
tCOP_DSP
Pipeline Register Clock to Output Time
-
4.80
-
5.89
-
6.87
ns
tCOO_DSP
Output Register Clock to Output Time
-
1.47
-
1.77
-
2.06
ns
tCOOVRFL_DSP
Overflow Register Clock to Output Time
-
1.47
-
1.77
-
2.06
ns
tSUADSUB
AdSub Setup Time
-
3.31
-
3.98
-
4.64
ns
tHADSUB
AdSub Hold Time
-
0.71
-
0.86
-
1.00
ns
tSUSIGN
Sign Setup Time
-
3.31
-
3.98
-
4.64
ns
tHSIGN
Sign Hold Time
-
0.80
-
0.96
-
1.12
ns
tSUACCSLOAD
Accumulator Load Setup Time
-
3.31
-
3.98
-
4.64
ns
tHACCSLOAD
Accumulator Load Hold Time
-
0.80
-
0.96
-
1.12
ns
1. Internal parameters are characterized but not tested on every device.
2. These parameters apply to LatticeECP devices only.
Rev F 0.17
LatticeECP/EC Internal Timing Parameters
1 (Continued)
Over Recommended Operating Conditions
Parameter
Description
-5
-4
-3
Units
Min.
Max.
Min.
Max.
Min.
Max.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com