LFEC datasheet(32/117 Pages) LATTICE

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Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Figure 2-33. LatticeECP/EC Banks

LatticeECP/EC devices contain two types of sysIO buffer pairs.

Top and Bottom sysIO Buffer Pair (Single-Ended Outputs Only)

The sysIO buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and

two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also be

conﬁgured as a differential input.

The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive

side of the differential input buffer and the comp (complementary) pad is associated with the negative side of

the differential input buffer.

Only the I/Os on the top and bottom banks have PCI clamp.

Left and Right sysIO Buffer Pair (Differential and Single-Ended Outputs)

The sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two

sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. The refer-

enced input buffer can also be conﬁgured as a differential input. In these banks the two pads in the pair are

described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O,

and the comp (complementary) pad is associated with the negative side of the differential I/O.

Only the left and right banks have LVDS differential output drivers.

Supported Standards

The LatticeECP/EC sysIO buffer supports both single-ended and differential standards. Single-ended standards

can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2,

1.5, 1.8, 2.5 and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually conﬁgurable

REF1(2)

GND

CCIO2

REF2(2)

REF1(3)

GND

CCIO3

REF2(3)

REF1(7)

GND

CCIO7

REF2(7)

REF1(6)

GND

Note: N and M are the maximum number of I/Os per bank.

CCIO6

REF2(6)

Bank 5

Bank 4

Bank 0

Bank 1

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