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Pinout Information_01.2

November 2004

Preliminary Data Sheet

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

Signal Descriptions

Signal Name

I/O

Descriptions

General Purpose

P[Edge] [Row/Column Number*]_[A/B]

I/O

[Edge] indicates the edge of the device on which the pad is located. Valid

edge designations are L (Left), B (Bottom), R (Right), T (Top).

[Row/Column Number] indicates the PFU row or the column of the device on

which the PIC exists. When Edge is T (Top) or (Bottom), only need to specify

Row Number. When Edge is L (Left) or R (Right), only need to specify Col-

umn Number.

[A/B] indicates the PIO within the PIC to which the pad is connected.

Some of these user-programmable pins are shared with special function

pins. These pin when not used as special purpose pins can be programmed

as I/Os for user logic.

During conﬁguration the user-programmable I/Os are tri-stated with an inter-

nal pull-up resistor enabled. If any pin is not used (or not bonded to a pack-

age pin), it is also tri-stated with an internal pull-up resistor enabled after

conﬁguration.

GSRN

Global RESET signal (active low). Any I/O pin can be GSRN.

—

No connect.

GND

—

Ground. Dedicated pins.

VCC

—Power supply pins for core logic. Dedicated pins.

VCCAUX

—

Auxiliary power supply pin. It powers all the differential and referenced input

buffers. Dedicated pins.

VCCIOx

—Power supply pins for I/O bank x. Dedicated pins.

VREF1_x, VREF2_x

—

Reference supply pins for I/O bank x. Pre-determined pins in each bank are

as assigned VREF inputs. When not used, they may be used as I/O pins.

XRES

—

10K ohm +/-1% resistor must be connected between this pad and ground.

PLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins)

[LOC][num]_PLL[T, C]_IN_A

Reference clock (PLL) input pads: ULM, LLM, URM, LRM, num = row from

center, T = true and C = complement, index A,B,C...at each side.

[LOC][num]_PLL[T, C]_FB_A

Optional feedback (PLL) input pads: ULM, LLM, URM, LRM, num = row from

center, T = true and C = complement, index A,B,C...at each side.

PCLK[T, C]_[n:0]_[3:0]

Primary Clock pads, T = true and C = complement, n per side, indexed by

bank and 0,1,2,3 within bank.

[LOC]DQS[num]

DQS input pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = ball

function number. Any pad can be conﬁgured to be output.

Test and Programming (Dedicated pins)

TMS

Test Mode Select input, used to control the 1149.1 state machine. Pull-up is

enabled during conﬁguration.

TCK

Test Clock input pin, used to clock the 1149.1 state machine. No pull-up

enabled.

LatticeECP/EC Family Data Sheet

Pinout Information

LFEC Datasheet(PDF) 63 Page - Lattice Semiconductor

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