LFEC datasheet(64/117 Pages) LATTICE

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Pinout Information

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

TDI

Test Data in pin. Used to load data into device using 1149.1 state machine.

After power-up, this TAP port can be activated for conﬁguration by sending

appropriate command. (Note: once a conﬁguration port is selected it is

locked. Another conﬁguration port cannot be selected until the power-up

sequence). Pull-up is enabled during conﬁguration.

TDO

Output pin. Test Data out pin used to shift data out of device using 1149.1.

VCCJ

—VCCJ - The power supply pin for JTAG Test Access Port.

Conﬁguration Pads (used during sysCONFIG)

CFG[2:0]

Mode pins used to specify conﬁguration modes values latched on rising edge

of INITN. During conﬁguration, a pull-up is enabled. These are dedicated

pins.

INITN

I/O

Open Drain pin. Indicates the FPGA is ready to be conﬁgured. During conﬁg-

uration, a pull-up is enabled. It is a dedicated pin.

PROGRAMN

Initiates conﬁguration sequence when asserted low. This pin always has an

active pull-up. This is a dedicated pin.

DONE

I/O

Open Drain pin. Indicates that the conﬁguration sequence is complete, and

the startup sequence is in progress. This is a dedicated pin.

CCLK

I/O

Conﬁguration Clock for conﬁguring an FPGA in sysCONFIG mode.

BUSY/SISPI

I/O

Read control command in SPI3 or SPIX mode.

CSN

sysCONFIG chip select (Active low). During conﬁguration, a pull-up is

enabled.

CS1N

sysCONFIG chip select (Active low). During conﬁguration, a pull-up is

enabled.

WRITEN

Write Data on Parallel port (Active low).

D[7:0]/SPID[0:7]

I/O

sysCONFIG Port Data I/O.

DOUT/CSON

Output for serial conﬁguration data (rising edge of CCLK) when using

sysCONFIG port.

DI/CSSPIN

Input for serial conﬁguration data (clocked with CCLK) when using sysCON-

FIG port. During conﬁguration, a pull-up is enabled.

Signal Descriptions (Cont.)

Signal Name

I/O

Descriptions

LFEC Datasheet(PDF) 64 Page - Lattice Semiconductor

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