68HC705JB3 datasheet(123/134 Pages) FREESCALE

123 / 134 page

November 5, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05JB3

ELECTRICAL SPECIFICATIONS

MOTOROLA

REV 1

13-5

13.6

CONTROL TIMING

NOTES:

The minimum period tILIL or tIHIH should not be less than the number of cycles it takes to execute the

interrupt service routine plus 19 tCYC.

Effects of processing, temperature, and supply voltage (excluding tolerances of external R and C)

tslow is a parameter dependent on fOSC and loading. Typical value of tslow is TENTATIVELY set at 170 ns

with minimal value of 130ns and maximal value of 185ns under the SIMULATION conditions that fOSC

is 6.0 MHz and slow output transition feature is enabled. Actual transition time will be speciﬁed to

replace the TBDs when enough characterization has been done on various wafers from different lots.

The values listed here represent data off simulation runs under the speciﬁed conditions. Under no cir-

cumstances should they be treated as the ﬁnal speciﬁcation.

Table 13-4. Control Timing

(VDD = 4.2V to 5.5V, VSS = 0 Vdc, TA = 0°C to +70°C, unless otherwise noted)

Characteristic

Symbol

Min

Max

Units

Frequency of Operation

Crystal Oscillator Option

External Clock Source

fOSC

—

MHz

Internal Operating Frequency

Crystal Oscillator (fOSC ÷ 2)

External Clock (fOSC ÷ 2)

fOP

—

MHz

Cycle Time (1/fOP)tCYC

330

—

RESET Pulse Width Low

tRL

1.5

—

tCYC

IRQ Interrupt Pulse Width Low (Edge-Triggered)

tILIH

0.5

—

tCYC

IRQ Interrupt Pulse Period

tILIL

note 1

—

tCYC

PA0 to PA3 Interrupt Pulse Width High

(Edge-Triggered)

tIHIL

0.5

—

tCYC

PA0 to PA3 Interrupt Pulse Period

tIHIH

note 1

—

tCYC

OSC1 Pulse Width

tOH, tOL

——

Output High to Low Transition Period on

PA6, PA7, PB0-4

tSLOW

Freescale Semiconductor, Inc.

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