AD8152 datasheet(16/32 Pages) AD

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REV. A

–16–

AD8152

RESET

DISABLING

OUT[0:33][N:P]

OUTPUTS

tTOD

tTW

Figure 5. Asynchronous Reset

Table IX. Asynchronous Reset

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tTOD

Disable Time

Output Disable from Reset

TA = 25 C10

25ns

tTW

Width of Reset Pulse

VCC = 3.3 V

CONTROL INTERFACE

The AD8152 control interface receives and stores the desired

connection matrix and output levels for the 34 input and 34 output

signal pairs. The interface consists of 34 rows of double-rank

6-bit latches, one for each output. The 6-bit data-word stored

in these latches indicates to which (if any) of the 34 inputs the

output will be connected, as well as the full-scale output current.

One output at a time can be preprogrammed by addressing the

output and writing the desired connection data or output cur-

rent into the first rank of latches. This process can be repeated

until each of the desired output changes has been preprogrammed.

All output connections can then be programmed at once by passing

the data from the first rank of latches into the second rank. The

output connections always reflect the data programmed into the

second rank of latches and do not change until the first rank of

data is passed into the second rank.

If necessary for system verification, the data in the second rank

of latches can be read back from the control interface.

At any time, a reset pulse can be applied to the control interface to

globally reset the appropriate second rank data bits, disabling all 34

signal output pairs and resetting the output currents. To facilitate

multiple chip address decoding, there is a chip select pin. All logic

signals except the reset pulse are ignored unless the chip select

pin is active. The chip select pin disables only the control logic

interface and does not change the operation of the signal matrix.

The chip select pin does not power down any of the latches, so any

data programmed in the latches is preserved.

All control pins are level-sensitive, not edge-triggered.

CONTROL PIN DESCRIPTION

A[6:0] Inputs

Output address pins. The binary encoded address applied to the

lower A[5:0] input pins determines which of the 34 outputs is

being programmed (or being read back). The most significant bit,

A6, determines whether the data pins contain information for

the connection register bank or the output level register bank.

Using the broadcast address, A[5:0] = “111111” will simulta-

neously program data into all outputs at once.

D[5:0] Inputs/Outputs

Input configuration or output level data pins. In write mode,

when the bank selection bit A6 is LOW, the binary encoded data

applied to pins D[5:0] determine which of the 34 inputs is to be

connected to the output specified with the A[5:0] pins. The most

significant bit is D5, and the least significant bit is D0. To disable

an output completely, the input address D[5:0] = “111111”

should be written into the input configuration bank at the desired

output address.

In write mode, when the bank selection bit A6 is HIGH, the

binary encoded data applied to pins D[3:0] indicate the output

current level to be used for the output specified with the A[5:0]

pins. The reset default is “0111” for 16 mA. Each LSB is 2 mA.

In readback mode, pins D[5:0] are low impedance outputs

indicating the data-word stored in the second rank for the out-

put specified with the A[5:0] pins and the bank specified with

the A6 bit. The readback drivers were designed to drive high

impedances only, so external drivers connected to the D[5:0]

should be disabled during readback mode.

WE Input

First rank write enable. Forcing this pin to logic low allows the

data on pins D[5:0] to be stored in the first rank latch for the

output specified by pins A[6:0]. The

WE pin must be returned to a

logic high state after a write cycle to avoid overwriting the first

rank data.

UPDATE Input

Second rank write enable. Forcing this pin to logic low allows the

data stored in all 34 first rank latches (in both banks) to be trans-

ferred to the second rank latches. The signal connection matrix

will be reprogrammed when the second rank data and levels are

changed. This is a global pin, transferring all 34 rows of data at

once. It is not necessary to program the address pins. It should

be noted that after initial power-up of the device, the first rank

data is undefined. It is desirable to preprogram all 17 outputs

before performing the first update cycle.

RE Input

Second rank read enable. Forcing this pin to logic low enables the

output drivers on the bidirectional D[5:0] pins, entering the read-

back mode of operation. By selecting an output address with the

A[6:0] pins and forcing

RE to logic low, the 6-bit data stored in

the second rank latch for that output address will be written to

D[5:0] pins. Data should not be written to the D[5:0] pins

externally while in readback mode. The

RE is a higher priority

pin than the

WE pin, so first rank programming is not possible

while in readback mode.

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