C8051F310 datasheet(160/224 Pages) ETC1

160 / 224 page

C8051F310/1/2/3/4/5/6/7

160

Rev. 1.6

15.1. Enhanced Baud Rate Generation

The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by

TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 15.2), which is not user-

accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.

The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an

RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to

begin any time a START is detected, independent of the TX Timer state.

Figure 15.2. UART0 Baud Rate Logic

Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “17.1.3. Mode 2: 8-bit

Counter/Timer with Auto-Reload” on page 185). The Timer 1 reload value should be set so that over-

flows will occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by

one of six sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, the external oscillator clock / 8, or

an external input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by

Equation 15.1.

Where T1CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload

value). Timer 1 clock frequency is selected as described in Section “17. Timers” on page 183. A quick

reference for typical baud rates and system clock frequencies is given in Table 15.1 through Table 15.6.

Note that the internal oscillator may still generate the system clock when the external oscillator is driving

Timer 1.

RX Timer

Start

Detected

Overflow

TH1

TL1

TX Clock

RX Clock

Timer 1

UART

Equation 15.1. UART0 Baud Rate

UartBaudRate

CLK

256

T1H

–

()

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