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Intel® 82845G/82845GL/82845GV GMCH Datasheet

5.1.3

AGP Memory Address Ranges

The GMCH can be programmed to direct memory accesses to the AGP bus interface when

addresses are within either of two ranges specified via registers in the GMCH’s Device 1

configuration space. The first range is controlled via the Memory Base Register (MBASE) and

Memory Limit Register (MLIMIT) registers. The second range is controlled via the Prefetchable

Memory Base (PMBASE) and Prefetchable Memory Limit (PMLIMIT) registers.

Conceptually, address decoding for each range follows the same basic concept. The top 12 bits of

the respective Memory Base and Memory Limit registers correspond to address bits A[31:20] of a

memory address. For the purpose of address decoding, the GMCH assumes that address bits

A[19:0] of the memory base are zero and that address bits A[19:0] of the memory limit address are

FFFFFh. This forces each memory address range to be aligned to 1-MB boundary and to have a

size granularity of 1 MB.

The GMCH positively decodes memory accesses to AGP memory address space as defined by the

following equations:

• Memory_Base_Address ≤ Address ≤ Memory_Limit_Address

• Prefetchable_Memory_Base_Address ≤ Address ≤ Prefetchable_Memory_Limit_Address

The window size is programmed by the plug-and-play configuration software. The window size

depends on the size of memory claimed by the AGP device. Normally these ranges will reside

above the Top-of-Main-DRAM and below High BIOS and APIC address ranges. They normally

reside above the top of memory (TOM) so they do not steal any physical SDRAM memory space.

It is essential to support a separate Prefetchable range to apply the USWC attribute (from the

processor point of view) to that range. The USWC attribute is used by the processor for write

combining.

Note that the GMCH Device 1 memory range registers described above are used to allocate

memory address space for any devices sitting on AGP that require such a window. These devices

would include the AGP device, PCI-66 MHz/1.5 V agents, and multifunctional AGP devices where

one or more functions are implemented as PCI devices.

The PCICMD1 register can override the routing of memory accesses to AGP. In other words, the

Memory Access Enable bit must be set in the Device 1 PCICMD1 register to enable the memory

base/limit and prefetchable base/limit windows.

845GL Datasheet(PDF) 146 Page - Intel Corporation