K32L3A datasheet(17/162 Pages) NXP

17 / 162 page

Table 5. Clock assignments (continued)

Module Name

Bus Interface

Clock

PCC Clock Gate

Peripherial

Functional Clock

Clock Domain1

I/O Interface

Clocks

I2S

BUS_CLK

Yes

SIRC_DIV2_CLK,

FIRC_DIV2_CLK,

LPFLL_DIV2_CLK

, SAI_MCLK

PCC03

SAI_TX_BCLK,

SAI_RX_BCLK,

SAI_MCLK

uSDHC

SYS_CLK

Yes

SIRC_DIV1_CLK,

FIRC_DIV1_CLK,

LPFLL_DIV1_CLK

, SDHC_DCLK

PCC0

SDHC_DCLK

LPSPI0~2

BUS_CLK

Yes

SIRC_DIV2_CLK,

FIRC_DIV2_CLK,

LPFLL_DIV2_CLK

PCC0

LPSPI0~2_SCK

LPSPI3

BUS_CLK

Yes

SIRC_DIV2_CLK,

FIRC_DIV2_CLK,

LPFLL_DIV2_CLK

PCC1

LPSPI3_SCK

LPUART0~2

BUS_CLK

Yes

SIRC_DIV2_CLK,

FIRC_DIV2_CLK,

LPFLL_DIV2_CLK

PCC0

—

LPUART3

BUS_CLK

Yes

SIRC_DIV2_CLK,

FIRC_DIV2_CLK,

LPFLL_DIV2_CLK

PCC1

—

USB

SYS_CLK

Yes

SIRC_DIV1_CLK,

FIRC_DIV1_CLK,

LPFLL_DIV1_CLK

PCC02

—

USB SRAM

SIRC_DIV1_CLK,

FIRC_DIV1_CLK,

LPFLL_DIV1_CLK

, SYS_CLK

Yes

—

PCC02

—

Human-Machine Interfaces

PORTA~D

SLOW_CLK

Yes

SLOW_CLK, LPO PCC0

—

PORTE

SLOW_CLK

Yes

SLOW_CLK, LPO PCC1

—

RGPIOA~D

PLAT_CLK

Yes

—

PCC0

—

RGPIOE

PLAT_CLK

Yes

—

PCC1

—

Analog

LPADC

BUS_CLK

Yes

SIRC_DIV2_CLK,

FIRC_DIV2_CLK,

LPFLL_DIV2_CLK

, LPADC Internal

Clock.

PCC0

—

LPCMP0

SLOW_CLK

—

SCG

—

LPCMP1

SLOW_CLK

—

SCG

—

LPDAC

BUS_CLK

Yes

—

PCC0

—

VREF

SLOW_CLK

Yes

—

PCC0

—

1. PPC0 controls CM4F domain,and PPC1 controls CM0+ domain.

2. It is bus interface clock domain.

3. SAI_MCLK doesn't blong to PCC clock domain.

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K32L3A, Rev. 1, 09/2019

NXP Semiconductors

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