K32L3A datasheet(7/162 Pages) NXP

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2.1 System features

The following sections describe the high-level system features.

2.1.1 Arm Cortex-M0+ core

The enhanced Arm Cortex M0+ is the member of the Cortex-M series of processors

targeting microcontroller cores focused on very cost sensitive, low power

applications. It has a single 32-bit AMBA AHB-Lite interface and includes an NVIC

component. It also has hardware debug functionality including support for simple

program trace capability. The processor supports the Arm v6-M instruction set

(Thumb) architecture including all but three 16-bit Thumb opcodes (52 total) plus

seven 32-bit instructions. It is upward compatible with other Cortex-M profile

processors.

This device supports hardware divider (MMDVSQ) when CM0+ core is working.

2.1.2 Arm Cortex-M4 core

The Cortex M4 processor is based on the Armv7 Architecture and Thumb®-2 ISA

and is upward compatible with the Cortex M3, Cortex M1, and Cortex M0

architectures. Cortex M4 improvements include an Armv7 Thumb-2 DSP (ported

from the Armv7-A/R profile architectures) providing 32-bit instructions with SIMD

(single instruction multiple data) DSP style multiply-accumulates and saturating

arithmetic.

2.1.3 NVIC

The Armv7-M exception model and nested-vectored interrupt controller (NVIC)

implement a relocatable vector table supporting many external interrupts, a single

non-maskable interrupt (NMI), and priority levels.

The NVIC replaces shadow registers with equivalent system and simplified

programmability. The NVIC contains the address of the function to execute for a

particular handler. The address is fetched via the instruction port allowing parallel

sources with the others mapping to MCU-defined interrupts.

Overview

K32L3A, Rev. 1, 09/2019

NXP Semiconductors

K32L3A Datasheet(PDF) 7 Page - NXP Semiconductors