K32L3A datasheet(8/162 Pages) NXP

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2.1.4 AWIC

The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is to

detect asynchronous wake-up events in stop modes and signal to clock control logic to

resume system clocking. After clock restart, the NVIC observes the pending interrupt

and performs the normal interrupt or event processing.

The device uses the following internal and external inputs to the AWIC module.

AWIC0 is AWIC in CM4F domain while AWIC1 is AWIC in CM0+ domain.

Table 2. AWIC0 Stop and VLPS wakeup sources

Wake-up source

Description

System resets

All available system resets sources are describted in SMC0

under MSMC chapter

SPM

All available interrupt in SPM, such as low/high voltage

detect interrupt, low voltage detect/warnning interrupt, and

etc.

PTA, PTB, PTC, PTD, PTE pin interrupts

LPUART0~3

Functional when using clock source which is active in Stop

and VLPS modes

LPI2C0~3

Address match wakeup

LPSPI0~3

Slave mode interrupt

I2S

Functional when using an external bit clock or external

master clock

EMVSIM

Any enabled interrupt can be a source as long as the module

remains clocked.

USB Controller

Wakeup

Secure Digital Hardware Controller (SDHC)

Wakeup

FlexIO

Functional when using clock source which is active in Stop

and VLPS modes

LPTMR0~2

Functional when using clock source which is active in Stop,

VLPS and LLS/VLLS modes

TPM0~3

Functional when using clock source which is active in Stop

and VLPS modes

RTC

Functional in Stop, VLPS, LLS and VLLSx modes

LPIT0/1

Any enabled interrupt can be a source as long as the module

remains clocked.

Tamper detect

Interrupt

NMI

NMI is routed to CM4F or CM0+ automatically, only boot

core has NMI

LPCMP0/1

Interrupt in normal or trigger mode

LPDAC

Any enabled interrupt can be a source as long as the module

remains clocked.

Table continues on the next page...

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K32L3A, Rev. 1, 09/2019

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