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K32L3A Datasheet(PDF) 6 Page - NXP Semiconductors |
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K32L3A Datasheet(HTML) 6 Page - NXP Semiconductors |
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6 / 162 page  USB2.0 Device w/ LS/FS PHY SDHC PORTA~D GPIO I2S DMA0 16CH DMAMUX0 64 CH EMVSIM PCC0 WDOG0 TRGMUX0 LPIT0 4CH CRC LPTPM0~2 LPTMR2 PCC1 WDOG1 TRNG GPIO LPTPM3 LPIT1 4CH LPUART3 LPI2C3 DMAMUX1 32 CH LPDAC 12-bit AWIC1 MTB CTI MPU NVIC SCB BP/WP TPIU CTI ETM AWIC0 DSP SCS Note: When a core needs access the other AXBS domain resources, the corresponding MUx_CCR[CLKE] bit must be set. AXBS keeps active even if another core enters low power mode (and CPO). FPB MPU DWT ITM NVIC DAP-AP LLWU0 DMA1 8 CH CAU3 LPTMR0~1 LLWU1 FlexIO 32 CH LPI2C0~2 LPSPI0~2 LPUART0~2 EWM TRGMUX1 M0 M2 M4 M1 M3 M5 S0 S1 S4 AIPS1 CM0+ I/D Flash 256 KB ROMC TSTMR1 I/D Cache (4 KB) Cortex M0+ (72 MHz –HSRun, 48 MHz –Run) I/D Cache (4 KB) CM4F I/D Flash 1 MB AXBS1 M0 M2 M3 S2 S0 S1 S3 Multi_Core Unit Clock SPM AXBS0 SWJ-DP BUS Interconnect IOPORT VBAT Register File 32B System Register File 32B LPADC 12 Bit LPDAC 12 Bit LPDAC 12-bit LPCMP0 w/ 6-bit DAC LPDAC 12-bit VREF 1.2/2.1V SEMA42 MU RDC xRDC SMC0 SMC1 MSMC Core Regulator IO Regulator DCDC RTC OSC 32 kHz SCG FIRC 48/52/56/60 MHz SIRC 2/8 MHz LPFLL MDM USB Regulator S2 FlexBus S3 LPCMP1 w/ 6-bit DAC RTC w/ Tamper Pin AIPS PORTE LPSPI3 M1 USB SRAM 2 KB SysTick SysTick AHB-AP DV/SQ RAMC TSTMR0 Cortex M4+FPU (72 MHz –HSRun, 48 MHz –Run) RAMC Figure 1. System diagram The crossbar switch connects bus masters and slaves using a crossbar switch structure. This structure allows up to four bus masters to access different bus slaves simultaneously for AXBS1 and up to six for AXBS0, while providing arbitration among the bus masters when they access the same slave. Overview 6 K32L3A, Rev. 1, 09/2019 NXP Semiconductors |
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