PMS152 datasheet(53/91 Pages) PADAUK

53 / 91 page

PMS152

8bit OTP Type SuLED IO Controller

Page 53 of 91

PDK-DS-PMS152-EN_V105 –Jun. 9, 2020

5.10. Interrupt

There are eight interrupt lines for PMS152:

 External interrupt PA0/PB5

 External interrupt PB0/PA4

 Timer16 interrupt

 GPC interrupt

 PWMG interrupt

 Timer2 interrupt

Every interrupt request line has its own corresponding interrupt control bit to enable or disable it; the hardware

diagram of interrupt function is shown as Fig.19. All the interrupt request flags are set by hardware and cleared

by writing intrq register. When the request flags are set, it can be rising edge, falling edge or both, depending

on the setting of register integs. All the interrupt request lines are also controlled by engint instruction (enable

global interrupt) to enable interrupt operation and disgint instruction (disable global interrupt) to disable it.

The stack memory for interrupt is shared with data memory and its address is specified by stack register sp.

Since the program counter is 16 bits width, the bit 0 of stack register sp should be kept 0. Moreover, user can

use pushaf / popaf instructions to store or restore the values of ACC and flag register to / from stack memory.

Since the stack memory is shared with data memory, the stack position and level are arranged by the compiler

in Mini-C project. When defining the stack level in ASM project, users should arrange their locations carefully to

prevent address conflicts.

Fig.19: Hardware diagram of interrupt controller

Once the interrupt occurs, its operation will be:

 The program counter will be stored automatically to the stack memory specified by register sp.

 New sp will be updated to sp+2.

 Global interrupt will be disabled automatically.

 The next instruction will be fetched from address 0x010.

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