PMS152 datasheet(3/91 Pages) PADAUK

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PMS152

8bit OTP Type SuLED IO Controller

Page 3 of 91

PDK-DS-PMS152-EN_V105 –Jun. 9, 2020

Table of content

1. Features ................................................................................................................................. 9

1.1.

Special Features .....................................................................................................................9

1.2.

System Features.....................................................................................................................9

1.3.

CPU Features .........................................................................................................................9

1.4.

Package Information ...............................................................................................................9

2. General Description and Block Diagram .......................................................................... 10

3. Pin Definition and Functional Description ....................................................................... 11

4. Device Characteristics ....................................................................................................... 17

4.1.

AC/DC Device Characteristics ..............................................................................................17

4.2.

Absolute Maximum Ratings...................................................................................................18

4.3.

Typical ILRC frequency vs. VDD ...........................................................................................19

4.4.

Typical IHRC frequency deviation vs. VDD(calibrated to 16MHz)..........................................19

4.5.

Typical ILRC Frequency vs. Temperature .............................................................................20

4.6.

Typical IHRC Frequency vs. Temperature (calibrated to 16MHz)..........................................20

4.7.

Typical operating current vs. VDD @ system clock = ILRC/n ................................................21

4.8.

Typical operating current vs. VDD @ system clock = IHRC/n ...............................................21

4.9.

Typical operating current vs. VDD @ system clock = 4MHz EOSC / n ..................................22

4.10.

Typical operating current vs. VDD @ system clock = 32KHz EOSC / n.................................22

4.11.

Typical operating current vs. VDD @ system clock = 1MHz EOSC / n ..................................23

4.12.

Typical IO driving current (IOH) and sink current (IOL) .............................................................23

4.13.

Typical IO input high/low threshold voltage (VIH/VIL) ..............................................................24

4.14.

Typical resistance of IO pull high device ...............................................................................25

4.15.

Typical power down current (IPD) and power save current (IPS)..............................................25

5. Functional Description....................................................................................................... 27

5.1.

Program Memory - OTP........................................................................................................27

5.2.

Boot Procedure .....................................................................................................................27

5.2.1. Timing charts for reset conditions.................................................................................28

5.3.

Data Memory - SRAM ...........................................................................................................29

5.4.

Oscillator and Clock ..............................................................................................................29

5.4.1.

Internal High RC oscillator and Internal Low RC oscillator .........................................29

5.4.2.

Chip calibration..........................................................................................................29

5.4.3.

IHRC Frequency Calibration and System Clock ........................................................30

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