W6100 datasheet(73/149 Pages) WIZNET

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W6100 – Hardwired Dual TCP/IP Stack Controller

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W6100 supports SPI mode 0 and mode 3 as shown in Figure 7 below.

Data is always sampling on the rising edge of SCLK and toggling on the falling edge of SCLK.

MOSI & MISO signals always transmit or receive in sequence from MSB to LSB every SCLK.

5.1.1 SPI Frame

W6100 communicates with HOST in SPI frame and SPI frame consists address phase, control

phase, and data phase as shown in Figure 8 below.

Address phase indicates 16bits offset address for W6100 register or TX/RX buffer. Control

phase indicates which block is selected, R/W access mode and SPI operation mode (VDM,

FDM). Data phase differs 1, 2, 4, N bytes by SPI operation mode.

When the SPI operation mode is Variable length Data Mode (VDM), CSn signal must be controlled

by the HOST. In the VDM, SPI frame starts by CSn transition (High –to –Low) of HOST and ends

by CSn transition (Low-to-High).

In brief, VDM is controlled by CSn and length is not limited. In FDM, the CSn value is fixed to ‘0’

and data transmits 1,2,4 bytes by SPI operation mode.

Figure 7 SPI Mode 0 & Mode 3

Figure 8 SPI Frame Format

W6100 Datasheet(PDF) 73 Page - WIZnet Co., Ltd