W6100 datasheet(81/149 Pages) WIZNET

Part #	W6100

Description	Hardwired Dual TCP/IP Stack Controller

PDF	149 Pages

Scroll/Zoom	100%

Manufacturer	WIZNET [WIZnet Co., Ltd]

Direct Link	https://www.wiznet.io/ko/Product/

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81 / 149 page

W6100 – Hardwired Dual TCP/IP Stack Controller

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SOCKET 2 TX Buffer

SOCKET 2 RX Buffer

111

Reserved

SOCKET 7 Register

SOCKET 7 TX Buffer

SOCKET 7 RX Buffer

IDM_DR

Indirect Mode Data Register

Data

5.2.1 Parallel BUS Data Write

Figure 18 Parallel BUS N-Bytes Data Write Access

Figure 18 shows N-Byte data write through parallel BUS. HOST asserts CSn to LOW during N-

bytes data transmission and if it is done, HOST de-asserts CSn to HIGH.

In write access, HOST should toggle WRn every BUS transition.

HOST transmits ‘00’ on ADDR[1:0] to indicate that ADDRH is on DAT[7:0], and then ‘01’ on

ADDR[1:0] & ADDRL on DAT[7:0], ‘10’ on ADDR[1:0] & BS on DAT[7:0], ‘11’ on ADDR[1:0] &

DATA on DAT[7:0].

If there are more than one byte DATA, ‘11’ on ADDR[1:0] and a DATA on DAT[7:0] can be

followed continuously.

W6100 Datasheet(PDF) 81 Page - WIZnet Co., Ltd