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W6100 Datasheet(PDF) 19 Page - WIZnet Co., Ltd

Part # W6100
Description  Hardwired Dual TCP/IP Stack Controller
PDF  149 Pages
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Manufacturer  WIZNET [WIZnet Co., Ltd]
Direct Link  https://www.wiznet.io/ko/Product/
Logo WIZNET - WIZnet Co., Ltd

W6100 Datasheet(HTML) 19 Page - WIZnet Co., Ltd

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W6100 – Hardwired Dual TCP/IP Stack Controller
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3.
W6100 Registers
3.1
Common Register
Offset
Register
Type1
Reset
0x0000
CIDR0 (Chip Identification Register)
RO
0x61
0x0001
CIDR1
RO
0x00
0x0002
VER0 (Chip Version Register)
RO
0x46
0x0003
VER1
RO
0x61
0x2000
SYSR (System Status Register)
RO
0xEU
0x2004
SYCR0 (System Config Register 0)
WO
0x80
0x2005
SYCR1
R=W
0x80
0x2016
TCNTR0 (Tick Counter Register)
RO
0x00
0x2017
TCNTR1
RO
0x00
0x2020
TCNTCLR (TCNTR Clear Register)
WO
0x00
0x2100
IR (Interrupt Register)
RO
0x00
0x2101
SIR (SOCKET Interrupt Register)
RO
0x00
0x2102
SLIR (SOCKET-less Interrupt Register)
RO
0x00
0x2104
IMR (Interrupt Mask Register)
R=W
0x00
0x2108
IRCLR (IR Clear Register)
WO
0x00
0x2114
SIMR (SOCKET Interrupt Mask Register)
R=W
0x00
0x2124
SLIMR (SOCKET-less Interrupt Mask Register)
R=W
0x00
0x2128
SLIRCLR (SLIR Clear Register)
WO
0x00
0x212C
SLPSR (SOCKET-less Prefer Source IPv6 Address Register)
R=W
0x00
0x2130
SLCR (SOCKET-less Command Register)
RW,AC
0x00
0x3000
PHYSR (PHY Status Register)
RO
0x00
0x3008
PHYRAR (PHY Register Address Register)
R=W
0x00
0x300C
PHYDIR0 (PHY Data Input Register)
R=W
0x00
0x300D
PHYDIR1
R=W
0x00
0x3010
PHYDOR0 (PHY Data Output Register)
RO
0x00
0x3011
PHYDOR1
RO
0x00
0x3014
PHYACR (PHY Access Control Register)
RW,AC
0x00
0x3018
PHYDIVR (PHY Division Register)
R=W
0x01
0x301C
PHYCR0 (PHY Control Register 0)
WO
0x00
0x301D
PHYCR1
R=W
0x40
0x4000
NET4MR (Network IPv4 Mode Register)
R=W
0x00
1 r
ef) 4. Register Descriptions



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