W6100 datasheet(74/149 Pages) WIZNET

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W6100 – Hardwired Dual TCP/IP Stack Controller

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5.1.1.1

Address Phase

Address phase indicates 16bits offset address of W6100 common register, SOCKET registers

and SOCKET n TX/RX buffer block.

The 16bits offset address is transferred from MSB to LSB sequentially.

W6100 SPI BUS interface supports sequential data read/write which offsets the address

automatically and increases by 1 after every 1byte read or write.

5.1.1.2

Control Phase

Control phase indicates the block to which the offset address in address phase belongs and

shows R/W access mode (RWB) and SPI operation mode (OM[1:0]).

BSB4

BSB3

BSB2

BSB1

BSB0

RWB

OM1

OM0

Bit

Symbol

Description

7~3

BSB

Block Selection Bits

W6100 has 1 common register, 8 SOCKET n register and TX/RX buffer

block for each SOCKET.

The block is selected by BSB[4:0] as shown in the table below.

The most significant three bits indicates SOCKET which is from 0 to 7.

The least significant two bits indicate what kind of subblocks are in the

SOCKET block.

BSB[4:2]

BSB[1:0]

Block

000

Common Register

SOCKET 0 Register

SOCKET 0 TX Buffer

SOCKET 0 RX Buffer

001

Reserved

SOCKET 1 Register

SOCKET 1 TX Buffer

SOCKET 1 RX Buffer

010

Reserved

SOCKET 2 Register

SOCKET 2 TX Buffer

SOCKET 2 RX Buffer

W6100 Datasheet(PDF) 74 Page - WIZnet Co., Ltd

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