W6100 datasheet(10/149 Pages) WIZNET

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W6100 – Hardwired Dual TCP/IP Stack Controller

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List of Figures

Figure 1 Block Diagram ........................................................................ 4

Figure 2 W6100 Pin Layout ................................................................. 12

Figure 3 W6100 Memory Map .............................................................. 17

Figure 4 State Diagram ...................................................................... 62

Figure 5 Variable Length Data Mode (CSn controlled by HOST) ..................... 72

Figure 6 Fixed Length Data Mode (CSn is always connected by Ground) .......... 72

Figure 7 SPI Mode 0 & Mode 3.............................................................. 73

Figure 8 SPI Frame Format ................................................................. 73

Figure 9 Write SPI Frame in VDM .......................................................... 76

Figure 10 Read SPI Frame in VDM ......................................................... 77

Figure 11 1 byte Data Write Access SPI Frame in FDM ................................ 78

Figure 12 2 bytes Data Write Access SPI Frame in FDM ............................... 78

Figure 13 4 bytes Data Write Access SPI Frame in FDM ............................... 78

Figure 14 1byte Data Read Access SPI Frame in FDM .................................. 79

Figure 15 2 bytes Data Read Access SPI Frame in FDM ................................ 79

Figure 16 4 bytes Data Read Access SPI Frame in FDM ................................ 79

Figure 17 HOST Interface in Parallel BUS Mode......................................... 80

Figure 18 Parallel BUS N-Bytes Data Write Access ..................................... 81

Figure 19 Parallel Mode Continuous Read Access ...................................... 82

Figure 20 TCP SERVER and TCP CLIENT .................................................. 85

Figure 21 TCP SERVER Operation Flow ................................................... 86

Figure 22 TCP CLIENT Operation Flow ................................................... 93

Figure 23 UDP Operation Flow ............................................................. 98

Figure 24 Received DATA in UDP Mode SOCKET RX Buffer Block.................... 99

Figure 25 IPv6 Multicast-Group Address Format....................................... 104

Figure 26 IPRAW Operation Flow ......................................................... 110

Figure 27 Received DATA in IPRAW4 Mode SOCKET RX Buffer Block .............. 111

Figure 28 Received DATA in IPRAW6 Mode SOCKET RX Buffer Block .............. 112

Figure 29 MACRAW Operation Flow ...................................................... 115

Figure 30 Received DATA Format in MACRAW ......................................... 116

Figure 31 SOCKET-less Command Operation Flow .................................... 117

Figure 32 DAD Operation Flow ............................................................ 124

Figure 33 RS Operation Flow .............................................................. 126

Figure 34 Unsolicited NA Operation Flow............................................... 129

Figure 35 MDC/MDIO Write Control Flow................................................ 135

Figure 36 MDC/MDIO Read Control Flow ................................................ 136

Figure 37 Quartz Crystal Model ........................................................... 138

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