AD4114

Data Sheet

Rev. 0 | Page 40 of 49

Bits

Bit Name

Settings

Description

Reset

Access

110000

Offset Register 0.

110001

Offset Register 1.

110010

Offset Register 2.

110011

Offset Register 3.

110100

Offset Register 4.

110101

Offset Register 5.

110110

Offset Register 6.

110111

Offset Register 7.

111000

Gain Register 0.

111001

Gain Register 1.

111010

Gain Register 2.

111011

Gain Register 3.

111100

Gain Register 4.

111101

Gain Register 5.

111110

Gain Register 6.

111111

Gain Register 7.

STATUS REGISTER

Address: 0x00, Reset: 0x80, Name: Status

The status register is an 8-bit register that contains ADC and serial interface status information. The register can optionally be appended

to the data register by setting the DATA_STAT bit in the interface mode register.

Table 21. Bit Descriptions for STATUS

Bits

Bit Name

Settings

Description

Reset

Access

7

RDY

The status of RDY is output to the DOUT/RDY pin when CS is low and a register is not

being read. This bit goes low when the ADC writes a new result to the data register. In

ADC calibration modes, this bit goes low when the ADC writes the calibration result.

RDY is brought high automatically by a read of the data register.

0x1

R

0

New data result available.

1

Awaiting new data result.

6

ADC_ERROR

By default, this bit indicates if an ADC overrange or underrange occurred. The ADC

result is clamped to 0xFFFFFF for overrange errors and 0x000000 for underrange

errors. This bit is updated when the ADC result is written and is cleared at the next

update after removing the overrange or underrange condition.

0x0

R

0

No error.

1

Error.

5

CRC_ERROR

This bit indicates if a CRC error occurred during a register write. For register reads, the

host microcontroller determines if a CRC error occurred. This bit is cleared by a read of

this register.

0x0

R

0

No error.

1

CRC error.

4

REG_ERROR

This bit indicates if the content of one of the internal registers changes from the value

calculated when the register integrity check is activated. The check is activated by

setting the REG_CHECK bit in the interface mode register. This bit is cleared by

clearing the REG_CHECK bit.

0x0

R

0

No error.

1

Error.