AD4114 datasheet(17/49 Pages) AD

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Data Sheet

AD4114

Rev. 0 | Page 17 of 49

Setup Configuration

The AD4114 has eight independent setups. Each setup consists

of the following four types of registers:



Setup configuration register



Filter configuration register



Gain register



Offset register

For example, Setup 0 consists of Setup Configuration Register 0,

Filter Configuration Register 0, Gain Register 0, and Offset

setup is selectable from the channel registers (see the Channel

Configuration section), which allows each channel to be assigned

to one of the eight separate setups. Table 10 through Table 13 show

the four registers that are associated with Setup 0. This structure is

repeated for Setup 1 to Setup 7.

Setup Configuration Registers

The setup configuration registers allow the user to select between

bipolar mode and unipolar mode to determine the ADC output

coding. The user can also select the reference source using these

registers. Three reference source options are available: a reference

connected between the REF+ and REF− pins, the internal

reference, or using AVDD – AVSS as the reference. The input

and reference buffers can also be enabled or disabled using

these registers.

Filter Configuration Registers

The filter configuration registers select which digital filter is

used at the output of the ADC modulator. Set the bits in these

registers to select the order of the filter and the output data rate.

For more information, see the Digital Filter section.

OFFSET REGISTERS

GAIN REGISTERS

SELECT PERIPHERAL

FUNCTIONS FOR

ADC CHANNEL

SELECT DIGITAL

FILTER TYPE

AND OUTPUT DATA RATE

INPUT BUFFERS

REFERENCE INPUT BUFFERS

REFERENCE SOURCE

31.25kSPS TO 2.5SPS

SINC5 + SINC1

SINC3

ENHANCED 50Hz OR 60Hz

SINC3 MAP

GAIN CORRECTION

OPTIONALLY

PROGRAMMED

PER SETUP AS REQUIRED

OFFSET CORRECTION

OPTIONALLY PROGRAMMED

PER SETUP AS REQUIRED

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

SETUPCON3

SETUPCON5

SETUPCON6

SETUPCON7

SETUPCON4

SETUPCON0

SETUPCON2

SETUPCON1

FILTCON3

FILTCON5

FILTCON6

FILTCON7

FILTCON4

FILTCON0

FILTCON2

FILTCON1

GAIN3

GAIN5

GAIN6

GAIN7

GAIN4

GAIN0

GAIN2

GAIN1

OFFSET3

OFFSET5

OFFSET6

OFFSET7

OFFSET4

OFFSET0

OFFSET2

OFFSET1

SETUP CONFIGURATION

REGISTERS

FILTER CONFIGURATION

REGISTERS

Figure 25. ADC Setup Register Grouping

Table 10. Setup Configuration Register 0

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1 Bit 0

Reset

R/W

0x20

SETUPCON0

[15:8]

Reserved

BI_UNIPOLAR0

REFBUF0+

REFBUF0−

INBUF0

0x1000

R/W

[7:0]

Reserved

REF_SEL0

Reserved

Table 11. Filter Configuration Register 0

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

R/W

0x28

FILTCON0

[15:8]

SINC3_MAP0

Reserved

ENHFILTEN0

ENHFILT0

0x0500

R/W

[7:0]

Reserved

ORDER0

ODR0

Table 12. Gain Register 0

Name

Bits

Bits[23:0]

Reset

R/W

0x38

GAIN0

[23:0]

GAIN0

0x5XXXX0

R/W

Table 13. Offset Register 0

Name

Bits

Bits[23:0]

Reset

R/W

0x30

OFFSET0

[23:0]

OFFSET0

0x800000

R/W

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