AD4114 datasheet(23/49 Pages) AD

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Data Sheet

AD4114

Rev. 0 | Page 23 of 49

BUFFERED REFERENCE INPUT

The AD4114 has true rail-to-rail, integrated, precision unity-gain

buffers on both ADC reference inputs. The buffers provide high

input impedance and allow high impedance external sources to

be directly connected to the reference inputs. The integrated

reference buffers can fully drive the internal reference switch

capacitor sampling network to simplify the reference circuit

requirements. Each reference input buffer amplifier is fully

chopped and minimizes the offset error drift and 1/f noise of the

buffer. When using a voltage reference, such as the ADR4525,

these buffers are not required because the reference has proper

decoupling and can drive the reference inputs directly.

CLOCK SOURCE

The AD4114 uses a nominal master clock of 2 MHz and can

source the device sampling clock from one of the following

three sources:



An internal oscillator.



An external crystal. Use a 16 MHz crystal automatically

divided internally to set the 2 MHz clock.



An external clock source.

All output data rates listed in this data sheet relate to a master clock

rate of 2 MHz. Using a lower clock frequency from, for instance,

an external source scales any listed data rate proportionally. To

achieve the specified data rates, particularly rates for rejection

of 50 Hz and 60 Hz, use a 2 MHz clock. To select the master

clock source, set the CLOCKSEL bits (Bits[3:2]) in the ADC

mode register, as shown in Table 14. The default operation on

power-up and reset of the AD4114 is to operate with the internal

oscillator. The user can use the SINC3_MAPx bits in the filter

configuration registers to fine tune the output data rate and

filter notch at low output data rates.

Internal Oscillator

The internal oscillator runs at 16 MHz and is internally divided

down to 2 MHz for the modulator. The internal oscillator can

be used as the ADC master clock and is the default clock source

for the AD4114, which is specified with an accuracy of −2.5% to

+2.5%.

The internal clock oscillator can be output on the XTAL2/

CLKIO pin. In this case, the clock output is driven to the

IOVDD logic level. This option can affect the dc AD4114

performance because of the disturbance introduced by the

output driver. The extent to which the performance is affected

depends on the IOVDD voltage supply. Higher IOVDD

voltages create a wider logic output swing from the driver and

affect performance to a greater extent. This effect is further

exaggerated if the IOSTRENGTH bit of the interface mode

External Crystal

If higher precision, lower jitter clock sources are required, the

AD4114 can use an external crystal to generate the master clock.

The crystal connects to the XTAL1 and XTAL2/CLKIO pins. The

FA-20H, a 16 MHz, 10 ppm, 9 pF crystal from Epson-Toyocom

is available in a surface-mount package and is acceptable for

this use. As shown in Figure 30, insert two capacitors (CX1 and

CX2) from the traces connecting the crystal to the XTAL1 and

XTAL2/CLKIO pins. These capacitors allow circuit tuning.

Connect these capacitors to the DGND pin. The value for these

capacitors depends on the length and capacitance of the trace

connections between the crystal and the XTAL1 and XTAL2/

CLKIO pins. Therefore, the values of these capacitors differ

depending on the PCB layout and the crystal used.

AD4114

XTAL1

CX1

1DECOUPLE TO DGND

CX2

XTAL2/CLKIO

Figure 30. External Crystal Connections

The external crystal circuitry can be sensitive to the SCLK edges

depending on the SCLK frequency, IOVDD voltage, crystal

circuitry layout, and the crystal used. During crystal startup,

any disturbances caused by the SLCK edges can cause double

edges on the crystal input, which results in invalid conversions

until the crystal voltage reaches a high enough level such that

any interference from the SCLK edges is insufficient to cause

double clocking. To avoid this double clocking, ensure that the

crystal circuitry reaches a sufficient voltage level after startup

before applying any serial clocks.

Because of the nature of the crystal circuitry, it is recommended

to perform empirical testing of the circuit under the required

conditions with the final PCB layout and crystal to ensure

correct operation.

External Clock

The AD4114 can also use an externally supplied clock. In systems

where an externally supplied clock is used, the external clock is

routed to the XTAL2/CLKIO pin. In this configuration, the

XTAL2/CLKIO pin accepts the externally sourced clock and

routes the clock input to the modulator. The logic level of this

clock input is defined by the voltage applied to the IOVDD pin.

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