VT6307 datasheet(25/54 Pages) VIA

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VT6307 PCI 1394a Host Controller

Revision 1.2 October 1, 2002

-19-

Technologies, Inc.

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Link Controller Configuration Registers (PCI Function 0)

The 1394 host controller interface follows the Open HCI

(OHCI) interface specification. There are two sets of software

accessible registers: configuration registers and memory

registers.

The configuration registers are located in the

function 0 PCI configuration space. The memory registers are

located in system memory space at offsets from the address

stored in the Base Address Register.

Configuration Space Header

Offset 1-0 - Vendor ID....................................................... RO

0-7

Vendor ID

................. (1106h = VIA Technologies)

Offset 3-2 - Device ID ........................................................ RO

0-7

Device ID

..... (3044h = VT6307 1394a Controller)

Offset 5-4 - Command ...................................................... RW

15-10 Reserved

........................................ always reads 0

Fast Back-to-Back Enable ........ fixed at 0 (disabled)

SERR# Enable ........................... fixed at 0 (disabled)

Wait Cycle Control ................... fixed at 0 (disabled)

Parity Error Response .............. fixed at 0 (disabled)

VGA Palette Snoop ................... fixed at 0 (disabled)

Postable Memory Write Enablefixed at 0 (disabled)

Special Cycle Enable ................. fixed at 0 (disabled)

Bus Master Enable

Disable................................................... default

Enable

Memory Space Enable

Disable................................................... default

Enable Access to 1394 Memory Registers

I/O Space Enable ....................... fixed at 0 (disabled)

Offset 7-6 - Status........................................................... RWC

Detected Parity Error.........................always reads 0

Signaled System Error .......................always reads 0

Received Master Abort

No Master Abort Generated................... default

Master Abort Generated by 1394 Controller.

Set by the 1394 interface logic if it generates a

master abort while acting as a master. This bit

may be cleared by software by writing a one to

this bit position.

Received Target Abort

No Target Abort Received ..................... default

Target Abort Received by 1394 Controller.

Set by the 1394 interface logic if it receives a

target abort while acting as a master. This bit

may be cleared by software by writing a one to

this bit position.

Signaled Target Abort........................always reads 0

10-9 DEVSEL# Timing

00 Fast

01 Medium.....................................................fixed

10 Slow

11 Reserved

Data Parity Error Detected ...............always reads 0

Fast Back-to-Back Capable ...............always reads 1

User Definable Features .....................always reads 0

66 MHz Capable .................................always reads 0

4-0

Reserved

........................................always reads 0

Offset 8 - Revision ID (nnh) ............................................... RO

7-0

Silicon Revision Code (0 indicates first silicon)

Offset 9 - Programming Interface (10h=OHCI) ............... RO

Offset A - Sub Class Code (00h=1394 Serial Bus) ............ RO

Offset B - Base Class Code (0Ch=Serial Bus Controller) .. RO

Offset D - Latency Timer (00h) ........................................ RW

7-4

Latency Timer Count

PCI burst cycles generated by the VT6307 can last

indefinitely as long as PCI GNT# remains active. If

GNT# is negated after the burst is initiated, the

VT6307 limits the duration of the burst to the number

of PCI Bus clocks specified in this field.

3-0

Reserved

........................................always reads 0

Offset E - Header Type (00h) ............................................ RO

VT6307 Datasheet(PDF) 25 Page - VIA Technologies, Inc.

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