VT6307 datasheet(27/54 Pages) VIA

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VT6307 PCI 1394a Host Controller

Revision 1.2 October 1, 2002

-21-

Technologies, Inc.

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Power Management Registers

Offset 50 – Capabilities ID (01h) ...................................... RO

7-0

Capabilities ID................................ always reads 01h

Always reads 01h to indicate that this list item is the

Power Management Register Block

Offset 51 – Next Item Pointer (00h) ................................. RO

7-0

Next Item Pointer ............................... always reads 0

Always reads 0 to indicate that there are no additional

items in the Capabilities List.

Offset 53-52 – Power Management Capabilities (E002) RO

PME# Can Be Asserted From D3cold

Not capable

Capable.....................................always reads 1

PME# Can Be Asserted From D3hot

Not capable

Capable.....................................always reads 1

PME# Can Be Asserted From D2

Not capable

Capable.....................................always reads 1

PME# Can Be Asserted From D1

Not capable ............................... always reads 0

Capable

PME# Can Be Asserted From D0

Not capable ............................... always reads 0

Capable

D2 Power Management State Supported

Not supported ........................... always reads 0

Supported

D1 Power Management State Supported

Not supported ........................... always reads 0

Supported

8-6

3.3V Auxiliary Current Required

000 None (device is self powered) ... always reads 0

001 55 mA

010 100 mA

011 160 mA

100 220 mA

101 270 mA

110 320 mA

111 375 mA

Device-Specific Initialization Required

Not required .............................. always reads 0

Required

Reserved

........................................ always reads 0

PME Clock

No PCI clock is required ........... always reads 0

PCI clock is required for PME# generation

2-0

Specification Version ................... always reads 010b

Reads 010b to indicate that this function complies

with Revision 1.1 of the PCI Power Management

Interface Specification

Offset 55-54 – Pwr Mgmt Control / Status (PMCSR) RWC

PME Status ......................................................RWC

This bit is set when the function would normally

assert the PME# signal independent of the state of the

PME_Enable bit. Writing a “1” will clear this bit and

cause the function to stop asserting PME# (if

enabled).

14-13 Data Scale

......................................................... RO

Scaling factor to use when interpreting the value of

the Data register....................................always reads 0

12-9 Data Select ........................................................ RW

Used to select which data is to be reported through

the Data register and Data_Scale field........default = 0

PME Enable ........................................................ RW

PME# assertion disabled........................ default

PME# assertion enabled

7-2

Reserved

........................................always reads 0

1-0

Power State ........................................................ RW

These bits indicate the current power state and are

used to change to a new power state. If an attempt is

made

write

code

corresponding

unsupported state, the write of these bits is ignored

and no state change occurs.

00 D0

01 D1

10 D2

11 D3hot

Offset 56 – Pwr Mgmt CSR Bridge Support Extensions RO

Bus Power / Clock Control Enable....always reads 0

B2/B3 Support for D3hot ...................always reads 0

5-0

Reserved

........................................always reads 0

Offset 57 – Power Management Data............................... RO

7-0

Data

Used to report state-dependent data requested by the

Data Select field of the PMCSR register (scaled per

the Data Scale field).

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