HT46C23 datasheet(11/48 Pages) HOLTEK

11 / 48 page

HT46R23/HT46C23

Rev. 1.60

May 3, 2004

Oscillator Configuration

There are two oscillator circuits in the microcontroller.

Both are designed for system clocks, namely the RC os-

cillator and the Crystal oscillator, which are determined

by options. No matter what oscillator type is selected,

the signal provides the system clock. The HALT mode

stops the system oscillator and ignores an external sig-

nal to conserve power.

If an RC oscillator is used, an external resistor between

OSC1 and VSS is required and the resistance must

range from 30k

W to 750kW. The system clock, divided

by 4, is available on OSC2, which can be used to syn-

chronize external logic. The RC oscillator provides the

most cost effective solution. However, the frequency of

oscillation may vary with VDD, temperatures and the

chip itself due to process variations. It is, therefore, not

suitable for timing sensitive operations where an accu-

rate oscillator frequency is desired.

If the Crystal oscillator is used, a crystal across OSC1

and OSC2 is needed to provide the feedback and phase

shift required for the oscillator, and no other external

components are required. Instead of a crystal, a resona-

tor can also be connected between OSC1 and OSC2 to

get a frequency reference, but two external capacitors in

OSC1 and OSC2 are required (If the oscillating fre-

quency is less than 1MHz).

The WDT oscillator is a free running on-chip RC oscilla-

tor, and no external components are required. Even if

the system enters the power down mode, the system

clock is stopped, but the WDT oscillator still works with a

period of approximately 65

ms@5V. The WDT oscillator

can be disabled by options to conserve power.

Watchdog Timer

- WDT

The clock source of the WDT is implemented by an dedi-

cated RC oscillator (WDT oscillator) or instruction clock

(system clock divided by 4) decided by options. This

timer is designed to prevent a software malfunction or

sequence jumping to an unknown location with unpre-

dictable results. The watchdog timer can be disabled by

an option. If the watchdog timer is disabled, all the exe-

cutions related to the WDT result in no operation.

Once an internal WDT oscillator (RC oscillator with pe-

riod 65

ms/@5V normally) is selected, it is divided by

12~215 (by options to get the WDT time-out period).

The minimum period of WDT time-out period is about

300ms~600ms. This time-out period may vary with tem-

perature, VDD and process variations. By selection the

WDT options, longer time-out periods can be realized. If

the WDT time-out is selected 2

15, the maximum time-out

period is divided by 2

15~216 about 2.1s~4.3s.

If the WDT oscillator is disabled, the WDT clock may still

come from the instruction clock and operate in the same

manner except that in the halt state the WDT may stop

counting and lose its protecting purpose. In this situation

the logic can only be restarted by external logic. If the

device operates in a noisy environment, using the

on-chip RC oscillator (WDT OSC) is strongly recom-

mended, since the HALT will stop the system clock.

The WDT overflow under normal operation will initialize

²chip reset² and set the status bit TO. Whereas in the halt

mode, the overflow will initialize a

²warm reset² only the

PC and SP are reset to zero. To clear the contents of WDT,

three methods are adopted; external reset (a low level to

RES), software instructions, or a HALT instruction. The

software instructions include CLR WDT and the other set

CLR WDT1 and CLR WDT2. Of these two types of instruc-

tion, only one can be active depending on the options

²CLR WDT times selection option².Ifthe ²CLR WDT² is

selected (i.e. CLRWDT times equal one), any execution of

the CLR WDT instruction will clear the WDT. In case

²CLR

WDT1

² and ²CLR WDT2² are chosen (i.e. CLRWDT times

equal two), these two instructions must be executed to

clear the WDT; otherwise, the WDT may reset the chip be-

cause of time-out.

If the WDT time-out period is selected fs/2

12 (by options),

the WDT time-out period ranges from fs/2

12~f

s/2

13, since

the

²CLR WDT² or ²CLR WDT1² and ²CLR WDT2² in-

structions only clear the last two stages of the WDT.

C r y s t a l O s c i l l a t o r

R C O s c i l l a t o r

O S C 1

O S C 2

N M O S O p e n D r a i n

O S C 2

f S Y S / 4

O S C 1

V D D

System Oscillator

f s / 2

S y s t e m C l o c k / 4

D i v i d e r

W D T P r e s c a l e r

M a s k O p t i o n

M a s k

o p t i o n

s e l e c t

W D T

O S C

f s

C K

T i m e - o u t R e s e t

f s / 2

~ f s / 2

f s / 2

~ f s / 2

f s / 2

~ f s / 2

f s / 2

~ f s / 2

1 5

1 6

W D T C l e a r

1 4

1 5

1 3

1 4

1 2

1 3

Watchdog Timer

HT46C23 Datasheet(PDF) 11 Page - Holtek Semiconductor Inc

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