HT46C23 datasheet(20/48 Pages) HOLTEK

20 / 48 page

HT46R23/HT46C23

Rev. 1.60

May 3, 2004

Low Voltage Reset

- LVR

The microcontroller provides low voltage reset circuit in

order to monitor the supply voltage of the device. If the

supply voltage of the device is within the range

0.9V~3.3V, such as changing a battery, the LVR will au-

tomatically reset the device internally.

The LVR includes the following specifications:

· The low voltage (0.9V~V

LVR) has to remain in their

original state to exceed 1ms. If the low voltage state

does not exceed 1ms, the LVR will ignore it and do not

perform a reset function.

· The LVR uses the

²OR² function with the external RES

signal to perform chip reset.

The relationship between VDD and VLVR is shown below.

Note: VOPR is the voltage range for proper chip

operation at 4MHz system clock.

2C Bus Serial Interface

2C Bus is implemented in the device. The I2C Bus is a

bidirectional two-wire lines. The data line and clock line

are implement in SDA pin and SCL pin. The SDA and

SCL are NMOS open drain output pin. They must con-

nect a pull-high resistor respectively.

Using the I

2C Bus, the device has two ways to transfer

data. One is in slave transmit mode, the other is in slave

receive mode. There are four registers related to I

Bus; HADR([20H]), HCR([21H]), HSR([22H]),

HDR([23H]). The HADR register is the slave address

setting of the device, if the master sends the calling ad-

dress which match, it means that this device is selected.

The HCR is I

2C Bus control register which defines the

device enable or disable the I

2C Bus as a transmitter or

as a receiver. The HSR is I

2C Bus status register, it re-

sponds with the I

2C Bus status. The HDR is input/output

data register, data to transmit or receive must be via the

HDR register.

The I

2C Bus control register contains three bits. The

HEN bit define the enable or disable the I

2C Bus. If the

data wants transfer via I

2C Bus, this bit must be set. The

HTX bit defines whether the I

2C Bus is in transmit or re-

ceive mode. If the device is as a transmitter, this bit must

be set to

²1². The TXAK defines the transmit acknowl-

edge signal, when the device received 8-bit data, the

device sends this bit to I

2C Bus at the 9th clock. If the re-

ceiver wants to continue to receive the next data, this bit

must be reset to

²0² before receiving data.

The I

2C Bus status register contains 5 bits. The HCF bit

is reset to

²0² when one data byte is being transferred. If

one data transfer is completed, this bit is set to

²1². The

HASS bit is set

²1² when the address is match, and the

2C Bus interrupt request flag is set to ²1². If the interrupt

is enabled and the stack is not full, a subroutine call to

location 10H will occur. Writing data to the I

2C Bus con-

7 6 t A D

A / D c o n v e r s i o n t i m e

7 6 t A D

A / D c o n v e r s i o n t i m e

0 0 0 B

1 0 0 B

0 1 0 B

0 0 0 B

S T A R T

E O C B

P C R 2 ~ P C R 0

A C S 2 ~ A C S 0

P o w e r - o n

R e s e t

E n d o f A / D

c o n v e r s i o n

1 : D e f i n e P B c o n f i g u r a t i o n

2 : S e l e c t a n a l o g c h a n n e l

1 . P B p o r t s e t u p a s I / O s

2 . A / D c o n v e r t e r i s p o w e r e d o f f

t o r e d u c e p o w e r c o n s u m p t i o n

A / D c l o c k m u s t b e f S Y S / 2 , f S Y S / 8 o r f S Y S / 3 2

N o t e :

S t a r t o f A / D

c o n v e r s i o n

R e s e t A / D

c o n v e r t e r

1 0 0 B

0 0 0 B

S t a r t o f A / D

c o n v e r s i o n

R e s e t A / D

c o n v e r t e r

A / D s a m p l i n g t i m e

3 2 t A D

M i n i m u m o n e i n s t r u c t i o n c y c l e n e e d e d

d o n ' t c a r e

A / D s a m p l i n g t i m e

3 2 t A D

E n d o f A / D

c o n v e r s i o n

A/D Conversion Timing

5 . 5 V

3 . 0 V

2 . 2 V

0 . 9 V

V D D

V O P R

V L V R

5 . 5 V

HT46C23 Datasheet(PDF) 20 Page - Holtek Semiconductor Inc

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