TMP139AIYAHT datasheet(32/58 Pages) TI

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Table 7-10. TMP139 Dynamic I/O Operation for I3C Mode (continued)

OPERATION

OPEN-DRAIN MODE PUSH-PULL MODE

PEC, T-bit sequence

Yes

7.4.8 Timing Diagrams

The TMP139 is a I2C and I3C interface-compatible device. Figure 6-1 to Figure 6-3 describe the various bus

conditions that are supported on the bus. The following lists the definitions for the bus conditions:

1. Bus Idle: Both SDA and SCL lines remain high after a Stop condition.

2. Start (S) condition: A change in the state of the SDA line from high to low, when the SCL is high defines a

Start condition. The Start condition is preceded by a bus idle.

3. Stop (P) condition: A change in the state of the SDA line from low to high, when the SCL is high defines a

Stop condition.

4. Repeated Start (SR) condition: A change in the state of the SDA line from high to low, when the SCL is high

and is preceded by a data transfer defines a Repeated Start condition.

5. Data Transfer: The number of data bytes transferred between a Start and Stop condition and determined by

the host or device.

6. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge (ACK) bit

during device address and host to device write transfer. A device that acknowledges must pull down the SDA

line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period

of the acknowledge clock pulse. On a host receive, the termination of the data transfer can be signaled by the

host generating a Not-Acknowledge (NAK) on the last byte that is transmitted by the target device. This

behavior is as per I2C mode of operation.

During I3C mode of operation. each receiving device shall only acknowledge its device address. Additionally,

the host shall acknowledge the device address during a successful IBI address arbitration.

7. T-Bit: The T-bit is only applicable in I3C mode of operation or when the host sends a common command

code (CCC) during I2C mode of operation. The T-bit contains the parity information when the host writes to

the targeted device(s). During a read, if the T-bit is sampled as 1 on the rising edge of the 9th clock, the bit

indicates a continuation of a read by the device. If a host wants to terminate the read, then the host can

activate the pullup while the device drives the line high as shown in Figure 6-2. When the device stops driving

the line and tri-states its output, the pull up keeps the line high momentarily before the host claims control of

the bus to generate a Repeated Start and Stop to end the read. If the host can accept more data from the

device, the host must not drive the line. The device samples the SDA on the falling edge of the 9th clock, and

if the T-bit is sampled as 1, the device resumes driving the SDA for the next byte. During a read, if the T-bit is

sampled as 0 on the rising edge of the 9th clock, the bit is used to indicate a termination of the read by the

device as shown in Figure 6-3. The host shall also drive the SDA low, such that when the device stops driving

the line and tri-states its output, the host has control of the bus to generate a Stop to end the read.

7.5 Programming

This section describes the programming model for specific operations of the TMP139.

7.5.1 Enabling Interrupt Mechanism

IBI can only be enabled in I3C basic mode. Figure 7-45 shows the programming model the host controller must

follow to correctly enable the IBI for the TMP139.

TMP139

SNIS217 – DECEMBER 2020

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