TMP139AIYAHT datasheet(14/58 Pages) TI

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If the SA pin is connected to GND, then the serial address for the TMP139 is encoded as 7'b0010111. If the SA

pin is connected to VDDSPD, then the serial address is encoded as 7'b0110111.

7.4.3 I2C Mode Operation

The I2C mode of operation is the primary mode of operation when the device is powered up, goes through a bus

reset, or when a RSTDAA CCC is issued if the device is in I3C mode of operation. The maximum bus speed

supported in this mode is up to 1.0 MHz. In this mode of operation, the following are not supported:

1. IBI: If IBI is enabled during I3C basic mode, then switching to I2C mode shall disable the IBI enabling

mechanism. If there are device events that cause the generation of IBI, then the status of the events shall be

logged by the device in the respective register.

2. Packet Error Check: This feature is not supported. If the host attempts to write data with a PEC byte, then the

PEC byte shall be treated as a data byte and written to the register address in an incremental format.

3. Parity Error Check: The parity error check is not supported except for the CCC that are listed in Table 7-6.

In the I2C mode of operation, the TMP139 supports SETHID, DEVCTRL and SETAASA CCC, and data transfer

packets without PEC. Additionally, a Start or Repeated Start followed by 7'h7E with W = 0 is only allowed for the

purpose of issuing the supported CCCs. Any other operation involving a Repeated Start shall be considered

illegal.

7.4.3.1 Host I2C Write Operation

For I2C write operation, the host controller sends the device address with R/W bit as 0, after a Start or Repeated

Start as shown in Figure 7-6. This is followed by the 8-bit register address and then the data. The TMP139 writes

the data to the register address specified. The internal write register address pointer is incremented after every

data byte written. If the write results in an address rollover, then the device shall reset the internal write register

address pointer and continue the write operation if possible. The TMP139 does not NACK the data byte for

reserved or read-only register, but shall discard the data byte and not update the register.

S or Sr

HID2

HID1

HID0

R/W=0

RA = Register Address [7:0]

ACK/NACK

Data(RA)

Data(RA+1)

...

ACK

Data(RA+N)

Sr or P

ACK

Figure 7-6. I2C Write Operation

7.4.3.2 Host I2C Read Operation

For I2C read operation, the host controller sends the device address with R/W bit as 0, after a Start or repeated

start. This is followed by the 8-bit register address. Once the register address is available to the TMP139, the

host issues a Repeated Start and sends the device address with R/W bit as 1. At this point the device shall send

the data from the register address incrementally, till the host sends a NACK. If the read operation results in the

internal read register address pointer to rollover, then the TMP139 device behavior is not defined.

TMP139

SNIS217 – DECEMBER 2020

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