TMP139AIYAHT datasheet(12/58 Pages) TI

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7.3.4 Bus Reset

The bus reset mechanism is supported by the TMP139, to prevent a device from locking up the serial bus. The

devices on the bus do not drive the SCL, therefore the bus reset mechanism uses the timeout scheme on the

SCL as shown in Figure 7-4. When the SCL is held low by the host controller for a time which is greater than

TTIMEOUT(max), TMP139 shall be reset and take the following action:

• Interface is reset, and as the bus reset is considered a Stop condition, any pending internal transaction is

also cleared.

• The TMP139 returns to I2C mode of operation, and resets the following registers:

– MR7 register, DEV_HID_CODE[2:0] is set to 3'b111.

– MR18 register, PEC_EN, PAR_DIS and INF_SEL are set to 1'b0.

– MR27 register, IBI_ERROR_EN is set to 1'b0.

– MR52 register, PEC_ERROR_STATUS and PAR_ERROR_STATUS are set to 1'b0.

• TMP139 does not resample the SA pin.

• TMP139 floats the SDA pin so that the bus controller can pull up the line.

SCL

tTIMEOUT(min)

tTIMEOUT(max)

Resets I

2C/I3C interface

Does not reset I

2C/I3C Interface

May or may not reset I

2C/I3C Interface

Figure 7-4. I2C or I3C Basic Bus Reset

7.3.5 Interrupt Generation

The TMP139 does not have a dedicated interrupt or alert pin, but instead supports interrupt generation using In

Band Interrupts (IBI) on the SDA pin. Interrupt generation using IBI is only supported during I3C mode of

operation. Hence the application must ensure that the device is first programmed to work in I3C mode before it

enables the IBI. As there are multiple devices on the I3C basic bus—each capable of generating an IBI—an

arbitration process is required.

The TMP139 generates an IBI only when it sees the bus in idle state for TAVAL. Once this condition is met, the

device pulls the SDA line low by TIBI_ISSUE to indicate to the host that it has an IBI. The host shall start by driving

the SCL low, which creates the Start bus condition. At this point the device shall send its device address on the

bus with the R/W bit set.

There can be a condition when the host starts a new bus transaction at the same time as the TMP139 is

generating an IBI. In such a case, the TMP139 shall arbitrate along with the host in the device address byte.

7.3.6 Parity Error Check

The parity error check implemented by the TMP139 is odd parity. In I2C mode, parity error check is not

supported except for supported common command codes (CCC). In I3C mode the parity error check is

supported for both CCC and host to device data transfers. The parity bit is only sent during the host write and the

TMP139 shall check the parity to ensure that the data or CCC it received is correct. The device implements odd

parity. If an odd number of bits in the byte are set as 1, the parity bit is set as 0. If an even number of bits in the

byte are set as 1, the parity bit is set as 1.

If there is a parity error during a data transfer or CCC, then the TMP139 shall drop the bytes after the parity error

is detected and shall wait for a Stop condition on the bus.

When a parity error is detected, the device shall set the IBI_STATUS bit in the MR48 register and

PAR_ERROR_STATUS bit in the MR52 register.

TMP139

SNIS217 – DECEMBER 2020

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