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TMP139AIYAHT Datasheet(PDF) 6 Page - Texas Instruments |
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TMP139AIYAHT Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 58 page  6.6 Timing Requirements minimum and maximum specifications are over –40 °C to 125 °C and VDDIO = 0.95 V to 1.05 V (unless otherwise noted)(1) I2C MODE - OPEN DRAIN I3C MODE - PUSH PULL(1) UNIT MIN MAX MIN MAX fSCL SCL operating frequency 0.01 1 0.001 12.5 MHz tHiGH Clock pulse width high time (Figure 6-1) 260 35 ns tLOW Clock pulse width low time (Figure 6-1) 500 35 ns tTIMEOUT Detect clock low timeout (Figure 7-4) 10 50 10 50 ms tR SDA rise time (Figure 6-1) 120 5 ns tF SDA fall time (Figure 6-1) 4 120 5 ns tSUDAT Data setup time (Figure 6-1) 50 8 ns tHDDI Data hold time(2) (Figure 6-1) 0 3 ns tSUSTA START condition setup time (Figure 6-1) 260 19.2 ns tHDSTA Hold time after repeated START condition. After this period, the first clock is generated. (Figure 6-1) 260 38.4 ns tSUSTO STOP condition setup time (Figure 6-1) 260 19.2 ns tBUF Time between STOP condition and next START condition (Figure 6-1) 500 500 ns tAVAL Bus available time (no edges seen in SDA and SCL) 1 µs tIBI_ISSUE Time to issue IBI after an event is detected when bus is available 15 µs tCLR_I3C_CMD_DELAY Time from Clear Register Status to any I3C operation with START condition. PEC disabled 4 µs Time from Clear Register Status to any I3C operation with START condition. PEC enabled 15 µs tHDDAT SCL falling clock in to SDA data out hold time (Figure 6-4) 0.5 350 ns tDOUT SCL falling clock in to SDA valid data out time (Figure 6-2, Figure 6-3, Figure 6-5) 0.5 12 ns tDOFFS SCL rising clock in to SDA output off (Figure 6-2, Figure 6-3) 0.5 12 ns tDOFFM SCL rising clock in to host controller SDA output off 0.5 30 ns tCL_R_DAT_F SCL rising clock in to host controller driving SDA low (Figure 6-2) 40 ns tDEVCTRLCCC_PEC_DIS DEVCTRL CCC followed by DEVCTRL CCC or register read/write command delay 3 3 µs tWR_RD_DECLAY_PEC_EN Register write command followed by register read command delay in PEC enabled mode 8 µs tI2C_CCC_UPDATE_DELAY SETHID CCC or SETAASA CCC to any other CCC or read/write command delay 2.5 µs tI3C_CCC_UPDATE_DELAY RSTDAA CCC or ENEC CCC or DISEC CCC to any other CCC or read/write command delay 2.5 µs tCCC_DELAY Any CCC to RSTDAA CCC delay 2.5 µs (1) The host and device have the same VDD value. Values are based on statistical analysis of samples tested during initial release. (2) The maximum t(HDDAT) can be 0.9 µs for fast mode, and is less than the maximum t(VDAT) by a transition time. 6.7 Switching Characteristics over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT tLPF Spike filter for I3C compatibility valid in I2C mode only SCL= 12.5 MHz 50 ns TMP139 SNIS217 – DECEMBER 2020 www.ti.com 6 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMP139 |
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