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TMP139AIYAHT Datasheet(PDF) 46 Page - Texas Instruments |
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TMP139AIYAHT Datasheet(HTML) 46 Page - Texas Instruments |
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46 / 58 page ![]() Table 7-35. MR51: Temperature Status Field Descriptions (continued) Bit Field Type Reset Description 0 TS_HIGH_STATUS R 0 Temperature sensor high status 0 = Temperature is below the limit set in registers MR29 and MR28. 1 = Temperature is above the limit set in registers MR29 and MR28. 7.6.24 MR52: Miscellaneous Error Status (address = 34h) [reset = 00h] The MR52 register stores the status for PEC checksum failure when PEC mode is enabled and parity error on the T-bit when the host writes to the device in I3C mode. Return to Register Map. Figure 7-70. MR52: Miscellaneous Error Status Register 7 6 5 4 3 2 1 0 Reserved PEC_ERROR_S TATUS PAR_ERROR_S TATUS R-00h R-0 R-0 Table 7-36. MR52: Miscellaneous Error Status Field Descriptions Bit Field Type Reset Description 7:2 Reserved R 00 Reserved 1 PEC_ERROR_STATUS R 0 Packet error status. 0 = No PEC error. 1 = PEC error in one or more packets. 0 PAR_ERROR_STATUS R 0 Parity check error status 0 = No parity error. 1 = Parity error in one or more bytes. TMP139 SNIS217 – DECEMBER 2020 www.ti.com 46 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMP139 |
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