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TMP139AIYAHT Datasheet(PDF) 39 Page - Texas Instruments |
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TMP139AIYAHT Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 58 page  7.6.8 MR19: Clear MR51 Temperature Status Command (address = 13h) [reset = 00h] The MR19 register is written by the host to clear status for the temperature comparison after the most recent conversion. Return to Register Map. Figure 7-54. MR19: Clear MR51 Temperature Status Command Register 7 6 5 4 3 2 1 0 Reserved CLR_TS_CRI T_LOW CLR_TS_CRIT _HIGH CLR_TS_LOW CLR_TS_HIGH R-0h R0-W1C R0-W1C R0-W1C R0-W1C Table 7-20. MR19: Clear MR51 Temperature Status Command Field Descriptions Bit Field Type Reset Description 7:4 Reserved R 0h Reserved 3 CLR_TS_CRIT_LOW R0-W1C 0 Clear temperature sensor critical low status 1 = Write '1' to clear MR51 TS_CRIT_LOW_STATUS bit Writing a '0' has no effect on MR51 TS_CRIT_LOW_STATUS bit 2 CLR_TS_CRIT_HIGH R0-W1C 0 Clear temperature sensor critical high status 1 = Write '1' to clear MR51 TS_CRIT_HIGH_STATUS bit Writing a '0' has no effect on MR51 TS_CRIT_HIGH_STATUS bit 1 CLR_TS_LOW R0-W1C 0 Clear temperature sensor low status 1 = Write '1' to clear MR51 TS_LOW_STATUS bit Writing a '0' has no effect on MR51 TS_LOW_STATUS bit 0 CLR_TS_HIGH R0-W1C 0 Clear temperature sensor high status 1 = Write '1' to clear MR51 TS_HIGH_STATUS bit Writing a '0' has no effect on MR51 TS_HIGH_STATUS bit 7.6.9 MR20: Clear MR52 Error Status Command (address = 14h) [reset = 00h] The MR20 register is written by the host to clear error condition when the PEC checksum is incorrect or when the last write from the host results in a parity error in the T-bit. This register is valid in I3C mode only. Return to Register Map. Figure 7-55. MR20: Clear MR52 Error Status Command Register 7 6 5 4 3 2 1 0 Reserved CLR_PEC_ERR OR CLR_PAR_ERR OR R-00h W1C W1C Table 7-21. MR20: Clear MR52 Error Status Command Field Descriptions Bit Field Type Reset Description 7:2 Reserved R 00h Reserved 1 CLR_PEC_ERROR R0-W1C 0 Clear packet error status 1 = Write '1' to clear MR52 PEC_ERROR_STATUS bit Writing a '0' has no effect on MR52 PEC_ERROR_STATUS bit 0 CLR_PAR_ERROR R0-W1C 0 Clear parity error status 1 = Write '1' to clear MR52 PEC_ERROR_STATUS bit Writing a '0' has no effect on MR52 PAR_ERROR_STATUS bit www.ti.com TMP139 SNIS217 – DECEMBER 2020 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: TMP139 |
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