TMP139AIYAHT datasheet(19/58 Pages) TI

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When IBI is enabled, the device can communicate to the host the error conditions seen, using IBI. However

when IBI is not enabled, it is strongly recommended that the host check the error status register to ensure that

no parity or PEC error was detected on the bus.

7.4.4.3 Host I3C Read Operation without PEC

As shown in Figure 7-15 and Figure 7-16, an I3C basic mode read is same as I2C read operation. For all bytes

sent by the device, the 9th bit is the T-bit, which is used by the device and host to negotiate continuation of the

read transfer. During the read phase, the device drives the T-bit as 1, before the rising edge to tell the host that it

can send more bytes or drives the T-bit as 0, to indicate to the host that the device wants to terminate the

transfer and the host shall respond with either a Stop or Repeated Start on the bus. The host may also terminate

the transfer by driving the T-bit as 0, only when device sends the T-bit as 1, which creates a repeated start

condition on the bus. Additionally, the host may send a Stop on the bus. When the IBI is enabled by the host, it

must send the IBI header byte which consists of 7'h7E+R/W = 0, before it sends the device address. This allows

the participating devices on the bus, to arbitrate between themselves if more than one device has an interrupt

condition that needs to be communicated to the host.

S or Sr

HID2

HID1

HID0

R/W=0

RA = Register Address [7:0]

ACK/NACK

Data(RA)

Data(RA+1)

...

T=1

Data(RA+N)

Sr or P

xxxxx

T=1

HID2

HID1

HID0

R/W=1

ACK/NACK

Figure 7-15. I3C Basic Mode Read

HID2

HID1

HID0

R/W=0

RA = Register Address [7:0]

ACK/NACK

Data(RA)

Data(RA+1)

...

T=1

Data(RA+N)

Sr or P

T=1

HID2

HID1

HID0

R/W=1

ACK/NACK

R/W=0

ACK

Figure 7-16. I3C Basic Mode Read with IBI Header

The TMP139 shall NACK the read phase of the transaction if there was a parity error in the write phase before

the repeated start. The device shall also send the T-bit as 0, if the host attempts to read data continuously such

that the internal read address pointer reaches 255, which is the last register in the register map table.

Additionally, if the host attempts to start a new transaction with a Repeated Start to the same device, when there

was a parity error in the previous transaction, then TMP139 shall NACK the device address to indicate an error

condition to the host. The host must first clear the parity error condition before performing any new transfer to the

TMP139. When IBI is enabled, the device can communicate to the host the error conditions seen, using IBI.

However when IBI is not enabled, it is strongly recommended that the host check the error status register to

ensure that no parity error was detected on the bus.

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TMP139

SNIS217 – DECEMBER 2020

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