F0502 datasheet(7/54 Pages) IDT

7 / 54 page

Sampling IF Receiver

1710MHz to 2050MHz

FlatNoise

TM, Zero-DistortionTM, SIF Rx

Rev2, January 2014

IDTF0552NLGI

Datasheet

F0552NBGI

Advance Datasheet

IDTF0552 SPECIFICATION

F0552 Typical Application Circuit, when operated as a Sampling IF Receiver, VCC = +5.00V, TC = +25°C, FRF = 1880

MHz, FIF = 184MHz, FLO = 1696MHz, PLO = 0 dBm, Output power = +3dBm per tone unless otherwise noted, TDD_A,

TDD_B = LOW. EVkit IF transformer losses are de-embedded unless otherwise noted.

Parameter

Comment

Symbol

min

typ

max

units

Logic Input High

For all control pins

VIH

1.07

Logic Input Low

For all control pins

VIL

0.68

Logic Current

For all control pins

IIH, IIL

-150

μA

Supply Current

Total VCC, STD Mode

ISTD

450

510

Supply Current

Total VCC, LC Mode

ILC

375

420

Supply Current

 Standby Mode

 STBY = VIH

 Total Both Channels

ISTBY

Gain STD Mode

Conversion Power Gain

Minimum attenuation

GSTDMAX

Gain LC Mode

Conversion Power Gain

Minimum attenuation

GLC

26.5

28.5

30.5

Gain control range

GRANGE

Gain STD mode min

gain setting

Maximum attenuation

GSTDMIN

-18

Step size

GSTEP

Differential Gain Error

Between any two adjacent

1dB steps

DNL

0.1

0.2

Integral Gain Error

Error vs. line (G27 Ref)

INL

0.2

0.8

Phase Error

Maximum phase change

between GMAX and any state

down to G-14

IPE

2.5

degree

NF STD Mode

Noise Figure (@ +25C)

NFSTD

9.6

10.6

NF STD Mode

10dB reduced gain

NFSTD_G-10

9.6

10.6

NF LC Mode

Noise Figure (@ +25C)

NFLC

9.3

10.3

NF LC Mode

10dB reduced gain

NFLC_G-10

9.5

10.5

NF w/Blocker

 +100 MHz offset blocker

 PIN = +4dBm

 28dB gain reduced

NFBLK

19.7

F0502 Datasheet(PDF) 7 Page - Integrated Device Technology

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