LAN7430 datasheet(37/77 Pages) MICROCHIP

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DS00002631D-page 37

LAN7430/LAN7431

6.7

Receive Filtering Engine (RFE)

The RFE receives Ethernet frames from the Ethernet MAC, processes them, and passes them to the RX FIFO Controller

(FCT). The RFE is responsible for filtering the received Ethernet frames, verifying the TCP/UDP/ICMP/IGMP and IP

checksum, and removing the VLAN tag.

When receiving a frame from the MAC, the RFE will obtain the frame data and status information. Upon completion of

frame processing, the RFE encapsulates its status with the status information obtained from the MAC, and passes this

information (along with the frame data) on to the FCT in the form of RX Command A, RX Command B, RX Command

C and RX Command D. The RFE also passes the receive timestamp from the 1588 module to the FCT.

The RFE, if enabled, can remove a VLAN tag from the frame. VLAN tag stripping is controlled by the Enable VLAN Tag

Stripping bit of the Receive Filtering Engine Control Register (RFE_CTL). If this bit is set, the tag will be stripped. If clear,

the RFE will not modify the frame in any way.

If multiple VLAN tags are present in a frame, the RFE only removes the first tag (adjacent to the MAC source address).

The RFE provides the Layer 3 Checksum (if enabled) and VLAN ID via RX Command B, while RX Command A, RX

Command C and RX Command D contain the frame’s status.

When the RFE determines a frame has a checksum error, it sets the appropriate error bits in RX Command A to identify

the error condition.

The FCT does not rewind frames that failed checksum validation from the FCT RX FIFO.

The RFE also determines the correct RX FCT channel in which to place the frame, based on various priorities methods

or MAC source or destination address or based on the Microsoft Receive Side Scaling specification. In order to minimize

delays through the RFE, data is processed on the fly and stored into all FIFOs in parallel. Once a determination is made

as to the correct destination FIFOs, the other FIFOs are instructed to drop the packet.

6.8

DMA Controller (DMAC)

The DMA Controller (DMAC) consists of independent receive (RX) and transmit (TX) DMACs, a series of arbiters, and

a control and status register space (CSRs). The TX DMAC transfers Ethernet frames from host memory to the FIFO

Controller (FCT), while the RX DMAC transfers Ethernet frames from the FCT to host memory. Both the RX and TX

DMACs have independent channels allocated to them (4 RX, 1 TX), through which the data transfer occurs.

Both the RX and TX DMACs utilize descriptors to efficiently move data from source to destination with minimal CPU

intervention. Descriptors are data structures in host memory that inform the DMAC of the location of data buffers in host

memory. In the case of the RX DMAC, it also provides a mechanism for communicating status to the CPU on completion

of DMA transactions. The host is responsible for setting up the descriptor rings and allocating RX descriptor buffers. TX

descriptor buffers are allocated and placed into the ring as needed. Each channel has its own descriptor ring and data

buffers. Descriptors are cached on chip to help absorb host bus latency.

The DMAC can be programmed to assert an interrupt for situations such as frame transmit or receive transfer com-

pleted, and other conditions.

6.9

FIFO Controller (FCT)

The FIFO controller uses internal RAMs to buffer RX and TX traffic. Host transmit data, via the DMAC, is directly stored

into the FCT TX FIFO(s). The FCT is responsible for extracting Ethernet frames from the host data and passing the

frames to the MAC.

Received Ethernet Frames are stored into the FCT RX FIFOs and become the basis for DMAC to host memory trans-

fers.

6.9.1

RX PATH (ETHERNET TO HOST)

The Receive direction buffer space consists of four parallel, independent channels. Each of the four 32 KB RX FIFOs

buffer Ethernet frames received from the RFE. The DMAC transfers these frames from the FCT to the host system mem-

ory. Host software will ultimately reassemble the Ethernet frames from the DMAC transfers.

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