LAN7430 datasheet(4/77 Pages) MICROCHIP

4 / 77 page

LAN7430/LAN7431

DS00002631D-page 4

 2018-2019 Microchip Technology Inc.

1.0

PREFACE

1.1

General Terms

TABLE 1-1:

GENERAL TERMS

Term

Description

1000BASE-T

1 Gbps Ethernet over twisted pair, IEEE 802.3 compliant

100BASE-TX

100 Mbps Ethernet over twisted pair, IEEE 802.3 compliant

10BASE-T

10 Mbps Ethernet over twisted pair, IEEE 802.3 compliant

ADC

Analog-to-Digital Converter

AFE

Analog Front End

AN, ANEG

Auto-Negotiation

AOAC

Always on Always Connected

ARP

Address Resolution Protocol

BELT

Best Effort Latency Tolerance

BYTE

8-bits

CSMA/CD

Carrier Sense Multiple Access/Collision Detect

CSR

Control and Status Register

Destination Address

DWORD

32-bits

Embedded Controller

EEE

Energy Efficient Ethernet

FCS

Frame Check Sequence

FIFO

First In First Out buffer

FSM

Finite State Machine

Firmware

GMII

Gigabit Media Independent Interface

GPIO

General Purpose I/O

HOST

External system (Includes processor, application software, etc.)

Hardware. Refers to function implemented by digital logic.

IGMP

Internet Group Management Protocol

LDO

Linear Drop-Out Regulator

Level-Triggered Sticky Bit

This type of status bit is set whenever the condition that it represents is asserted. The

bit remains set until the condition is no longer true, and the status bit is cleared by

writing a zero.

LFSR

Linear Feedback Shift Register

LPM

Link Power Management

lsb

Least Significant Bit

LSB

Least Significant Byte

LTM

Latency Tolerance Messaging

MAC

Media Access Controller

MDI

Medium Dependent Interface

MDIX

Media Independent Interface with Crossover

MEF

Multiple Ethernet Frames

MII

Media Independent Interface

MLT-3

Multi-Level Transmission Encoding (3-Levels). A tri-level encoding method where a

change in the logic level represents a code bit “1” and the logic output remaining at

the same level represents a code bit “0”.

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