LAN7430 datasheet(40/77 Pages) MICROCHIP

40 / 77 page

LAN7430/LAN7431

DS00002631D-page 40

 2018-2019 Microchip Technology Inc.

6.12.1

POWER-ON RESET (POR)

A Power-On Reset (POR) occurs whenever power is initially applied to the device, or if power is removed and reapplied

to the device. A timer within the device will assert the internal reset for approximately 20 ms. EEPROM/OTP contents

are loaded by this reset. Configuration straps are also loaded by this reset.

The POR is a combination of four separate POR circuits that measure the voltage on the following domains:

• 3.3V to 1.8V (set for 1.8V typical) - VDDVARIO, VDDVARIO_B

•1.2V - AVDD12, AVDDL_1, AVDDL_2, VPTX, VP, VDD12CORE (monitored on AVDD12 and VDD12CORE)

•2.5V - VPH, AVDDH_1, AVDDH_2 (monitored on VDD25_REG_OUT)

•3.3V - VDD_OTP, AVDDH_1, AVDDH_2 (monitored on VDD_OTP)

6.12.2

EXTERNAL CHIP RESET (RESET_N)

A hardware reset will occur when the RESET_N pin is driven low. Assertion of RESET_N is not required at power-on.

However, if used, RESET_N must be driven low for a minimum period as defined in Section 7.6.4, "Reset Pin Configu-

ration Strap Timing". The RESET_N pin is not pulled-high internally and must be connected to VDDVARIO if unused.

6.12.3

PCIE FUNDAMENTAL RESET

The PCIe fundamental reset uses the PERST# pin, which indicates that the PCIe main power and reference clock are

valid. It is used as a cold reset when the device operates from the main PCIe power source. It is used as a warm reset

when the device operates from the auxiliary PCIe power source and indicates, to the still powered and operational

device, that the main power and / or reference clock are not valid.

6.12.3.1

Warm Reset

A warm reset occurs when the device is operating on auxiliary power or multiplexed main / auxiliary power (VAUX_DET

pin = 1) and PERST# is asserted. The device enters the D3cold state. Warm reset is normally preceded by the PCIe link

being placed into the L2/L3 Ready state. The D3cold state is exited when PERST# deasserts.

6.12.4

HOT RESETS

Hot resets include

• An in-band mechanism for propagating Conventional Reset across a Link

• An in-band mechanism for software to force a Link into Electrical Idle, disabling the Link

• The Data Link Layer reporting DL_Down status.

6.12.5

FUNCTION-LEVEL RESET (FLR)

Function-Level Reset is a software issued reset triggered when the Initiate Function Level Reset bit in the PCIe Device

Control configuration register is set. It is used to reset the device without affection the link state. An FLR starts, is pro-

cessed and then exits.

During an FLR:

• All requests and completions for the function that arrived from the wire before the FLR started are handled by

silently dropping them.

• All requests following the FLR are discarded using Unsupported Request (UR) (for posted and non-posted

requests), and using Unexpected Completion (UC) for completions. Therefore, the software driver should put the

function into a quiescent state (by clearing the BME or otherwise) before initiating an FLR so that the function

does not issue requests in close proximity to the FLR event. Otherwise, any completions from these requests will

dropped later on.

• The function should not issue requests during FLR. Otherwise, completions from these requests (received by the

device after the function has exited FLR) are treated as unexpected and dropped.

• Any outstanding INTx interrupt asserted by the function must be deasserted by sending the corresponding Deas-

sert_INTx Message.

Note:

If configured, the EEPROM/OTP contents are reloaded by this reset. The configuration straps are also

loaded by this reset.

Note:

Resets occur on the release of PERST#, not on the active level.

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