LAN7430 datasheet(42/77 Pages) MICROCHIP

42 / 77 page

LAN7430/LAN7431

DS00002631D-page 42

 2018-2019 Microchip Technology Inc.

6.13

Power Management

The device supports two categories of Power Management (PM) operations to control the device state (D-state) and

link state of the PCIe PHY and Endpoint Controller functional blocks.

Software PCI Compatible PM (PCI-PM) allows the host software to direct the function to enter into the D3hot and D3cold

low-power states. This indirectly causes a change in the link power state. The L1 state is entered when the device is

programmed to a non-D0 state. Further entry into L1.1 and L1.2 sub-states is initiated by the downstream port. Clock

power management during the L1 state provides for the removal of the PCIe reference clock.

Native PCIe PM Mechanisms include Active State PM (ASPM) which, while in the L0 state, detects idle on the link for a

specific time duration and automatically transitions the link to the L0s or L1 power states. L1 Sub-states are also sup-

ported that disables components on a link to further reduce idle power consumption while the link is in the L1 state,

including almost complete removal of power for the high speed PHY circuits.

The power management functions include:

• Enabling the host to place the device in a reduced power state, by selectively disabling internal clocks and power-

ing down the Ethernet PHY (LAN7430 only).

• Providing for detection of various wakeup events.

• Providing a host-readable READY flag which is set when the device is fully operational.

• Controlling the loading of OTP or EEPROM values after a system reset.

• Supporting D0 and D3hot and D3cold states

• Supporting L0s, L1 states and L1.1 and L1.2 Sub-states

Power Management Event (PME) functions include:

• Supporting PCIe WAKE# and Beaconing.

• Supporting PCIe PME Messaging.

• Supporting GPIO, Link Change, Ethernet Frame as sources for wakeup.

6.13.1

PCIe DEVICE STATES

The device supports the mandatory D0 (herein referred to as D0u (uninitialized), D0a (active)), D3hot, and D3cold power

states. The optional D1 and D2 states are not support by the device.

The device can signal a wake event detection by sending a PME message and asserting wakeup via Beaconing and

the WAKE# pin. The PME messaging can be generated in all states, except the D0u and D3cold state. Wakeup via Bea-

coning and the WAKE# pin can be generated in all states, including the D3cold state, except D0u.

The device can send PME messaging and assert wakeup upon detection of various power management events, such

as an Ethernet “Wake On LAN”, Energy Efficient Ethernet activity, PHY link and energy detection and GPIO events. As

a result, the host can reconfigure the power management state.

As a single function device, the device implements power management capabilities and power management control/

status registers, which are mapped into the PCIe configuration space. The PME_Support and Aux_Current fields of the

Power Management Capabilities register is dependent on the setting of the external VAUX_DET pin. The Data_Scale

and Data_Select fields of the Power Management Capabilities register will always return zero, as the Data Register is

not implemented.

The descriptions that follow refer to the “PME Context”. PME Context is defined as:

• The PME_Status and PME_En fields in the PCIe Power Management Control/Status configuration register

• The Aux Power PM Enable field in the PCIe Device Control configuration register

• The Wakeup Source Register (WK_SRC) register

Device power management states are directly controlled by software by writing the Power State field in the PCIe Power

Management Control/Status configuration register.

In addition, the device utilizes two control signals. These are PERST#, to determine when main power is valid, and

VAUX_DET to determine if auxiliary power exists.

Note:

If alternate usage of the VAUX_DET pin (e.g. GPIO3, LED3 or TMS) is enabled, the input value of the pin

is overridden to a low value.

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