AD4696 datasheet(32/96 Pages) AD

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AD4695/AD4696

Data Sheet

Rev. 0 | Page 32 of 96

TEMPERATURE SENSOR

The AD4695/AD4696 include a temperature sensor that

converts the die temperature to an output voltage that can be

sampled and converted to an output code by the SAR ADC core.

The relationship between the measured die temperature (T) and

the temperature sensor output voltage (VTEMP) is nominally

25 m

TEMP



















The temperature sensor sensitivity is a measure of the change

in output voltage in relation to a change in device temperature,

and is typically −1.8 mV/°C. At 0°C, the temperature sensor

output is typically 725 mV.

When the temperature sensor is selected, the multiplexer

SWMUX+ switch (see Figure 65) selects the temperature sensor

output and its SWMUX− switch selects REFGND, and the SAR

ADC core samples VTEMP to generate a corresponding output

code. The analog-to-digital conversion of the temperature

sensor output utilizes the same transfer function as an analog

input configured in unipolar mode with OSR = 1 (see the

Transfer Function section).

When the standard sequencer or advanced sequencer is

enabled, the temperature sensor is sampled at the end of the

preprogrammed channel sequence if the TEMP_EN bit in the

TEMP_CTRL register is set to 1.

When using either two-cycle command mode or single-cycle

command mode, the temperature sensor can be selected by

writing the code 0x0F on SDI on the first five rising edges of

SCK in the same way analog inputs are selected (see Table 16).

When the temperature sensor is enabled, analog input high-Z

mode is always enabled and the OSR is always 1. The

temperature sensor does not have threshold detection alerts.

VOLTAGE REFERENCE INPUT

VREF sets the ADC full-scale voltage (see the Transfer Function

section). The ADC core samples the voltage on the reference input

(REF) during the bit trials in the conversion process to determine

the output code result. The AD4695/AD4696 are compatible with

reference voltages from 2.4 V to 5.1 V.

The AD4695/AD4696 must be configured for optimal

performance with the selected reference voltage. The VREF_SET

field in the REF_CTRL register provides five VREF range options,

as shown in Table 46. This value must be programmed to

match the VREF voltage applied to the REF pin.

A common challenge presented by traditional SAR ADCs is in

designing reference circuitry with sufficient drive capability to

maintain a precise VREF while the REF input dynamically draws

input current during the SAR bit trials. Deviations in VREF result

in reduction in ADC accuracy and performance, such as higher

gain error or distortion. The REF input presents a dynamic load as

the input pulls charge from the external reference circuitry at

different times in the SAR process. This process traditionally

requires either voltage references with sufficient load regulation

and drive capabilities, or the use of a dedicated reference buffer

to drive the REF input with a large reference decoupling capacitor.

See the Reference Circuitry Design section for more information

on properly selecting reference circuitry components.

The AD4695/AD4696 incorporate features that simplify design

of the companion reference circuitry, and facilitate the design

of small footprint, low power systems. The reference input

high-Z mode reduces the REF input current by approximately

95%, allowing a broader selection of voltage references and

amplifiers to drive the REF input without impacting performance

(see the Reference Input High-Z Mode section).

The reference input current scales with sample rate (see Table 1

and Figure 39).

Reference Input High-Z Mode

When enabled, reference input high-Z mode reduces the average

REF current by approximately 95% from 320 μA/MSPS to 11

μA/MSPS. The reduction in REF current allows the AD4695/

AD4696 to tolerate larger series resistance between the reference

source and the REF input without compromising performance.

Therefore, reference input high-Z mode allows voltage references

with higher load regulation specifications to directly drive the REF

input without the need for a dedicated reference buffer.

The REF input requires a reference decoupling capacitor (CREF).

When reference input high-Z mode is disabled, CREF must be

10 μF or larger. When reference input high-Z mode is enabled,

CREF can be as small as 1 μF.

See the Reference Circuitry Design section for more reference

circuit design recommendations.

To enable and disable reference input high-Z mode, set the

value of the REFHIZ_EN bit in the REF_CTRL register.

Reference input high-Z mode is enabled by default.

Analog input high-Z mode must be enabled when reference

input high-Z mode is enabled. If any analog input channels are

configured with analog input high-Z mode disabled, reference

input high-Z mode must also be disabled.

POWER SUPPLIES

The AD4695/AD4696 have three power supply pins: an analog

supply (AVDD), an ADC core supply (VDD), and a digital

input/output interface supply (VIO). The AD4695/AD4696

also include an internal LDO that can be used to provide the

VDD rail with a wider variety of supply voltages (or in single-

supply systems by tying LDO_IN to AVDD). Table 1 shows the

specified power supply voltage requirements.

AVDD can range from 3.15 V to 5.5 V and powers the analog

front-end features of the AD4695/AD4696, including the analog

input high-Z mode and reference input high-Z mode circuitry.

VDD is nominally 1.8 V, and powers both the ADC core and the

device register memory. When power is first applied to VDD, the

ADC core initializes and the device register contents are set to the

default states (as shown in the Register Information section).

AD4696 Datasheet(PDF) 32 Page - Analog Devices

AD4696 Datasheet(HTML) 32 Page - Analog Devices

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