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AD4696 Datasheet(PDF) 8 Page - Analog Devices |
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AD4696 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 96 page  AD4695/AD4696 Data Sheet Rev. 0 | Page 8 of 96 TIMING SPECIFICATIONS AVDD= 3.15 V to 5.5 V, LDO_IN = 2.4 V to 5.5 V with internal LDO enabled, LDO_IN = AGND with internal LDO disabled, VDD = 1.71 V to 1.89 V with internal LDO disabled, VIO = 1.14 V to 1.98 V, AGND = REFGND = IOGND = 0 V, reference voltage (VREF) = 2.4 V to 5.1 V, REF = VREF, fS = 1 MSPS for the AD4696, fS = 500 kSPS for the AD4695, digital output load capacitance = 20 pF, autocycle mode disabled, no active overvoltage protection clamps, and TA = −40°C to +125°C, unless otherwise noted. Table 2. Parameter1 Symbol Min Typ Max Unit Conversion Time tCONVERT 380 415 ns Acquisition Time tACQ Two-Cycle Command Mode, Standard Sequencer, or Advanced Sequencer Enabled fS = 1 MSPS 715 ns fS = 500 kSPS 1715 ns Single-Cycle Command Mode2 Enabled CNV Period (Time Between Conversions) tCYC fS = 1 MSPS, Autocycle Mode Disabled 1000 ns fS = 500 kSPS, Autocycle Mode Disabled 2000 ns Autocycle Mode Enabled AC_CYC = 0x0 8.5 10 11.5 μs AC_CYC = 0x1 17 20 23 μs AC_CYC = 0x2 34 40 46 μs AC_CYC = 0x3 68 80 92 μs AC_CYC = 0x4 85 100 115 μs AC_CYC = 0x5 170 200 230 μs AC_CYC = 0x6 340 400 460 μs AC_CYC = 0x7 680 800 920 μs CNV High Time tCNVH 10 ns CNV Low Time tCNVL 80 ns CS High Time tCSBH 5 ns CS Low to Digital Interface Ready Delay tEN 15 ns CS High to SDO High Impedance Delay tCSBDIS 15 ns SCK Period tSCK Register Configuration Mode 40 ns Conversion Mode 12.5 ns SCK Low Time tSCKL Register Configuration Mode 16 ns Conversion Mode 5 ns SCK High Time tSCKH Register Configuration Mode 16 ns Conversion Mode 5 ns SDI Data Setup Time Prior to SCK Rising Edge tSSDI 2 ns SDI Data Hold Time After SCK Rising Edge tHSDI 2 ns SCK Falling Edge to Data Remains Valid Delay tHSDO 1.5 ns SCK Falling Edge to Data Valid Delay tDSDO 10.5 ns Last SCK Edge to CNV Rising Edge Delay tSCKCNV 80 ns Last SCK Rising Edge to CS Rising Edge Delay tSCKCSB 1 ns CNV Rising Edge to Busy Indicator Rising Edge (Busy Indicator Enabled on General-Purpose Pin) tCNVBSY 20 ns CNV Rising Edge to Alert Indicator Transition (Alert Indicator Enabled on General-Purpose Pin) tCNVALT 425 ns Busy Indicator Low Time, Autocycle Mode Enabled (Busy Indicator Enabled on General-Purpose Pin) tACBSY AC_CYC = 0x0 8 µs AC_CYC = 0x1 16.5 µs AC_CYC = 0x2 33.5 µs AC_CYC = 0x3 67.5 µs AC_CYC = 0x4 84.5 µs |
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