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AD4696 Datasheet(PDF) 9 Page - Analog Devices |
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AD4696 Datasheet(HTML) 9 Page - Analog Devices |
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9 / 96 page ![]() Data Sheet AD4695/AD4696 Rev. 0 | Page 9 of 96 Parameter1 Symbol Min Typ Max Unit AC_CYC = 0x5 169 µs AC_CYC = 0x6 339 µs AC_CYC = 0x7 679 µs Register Configuration Mode Setup Time tREGCONFIG 20 ns RESET Low Time tRESETL 10 ns Hardware Reset Delay (VDD Always Supplied) tHWR_DELAY 310 µs Software Reset Delay tSWR_DELAY 310 µs VDD Power-On Reset Delay tPOR_VDD 2 ms VIO Power-On Reset Delay (VDD Supplied Externally) tPOR_VIO1 1.3 ms LDO_IN Power-On Reset Delay tPOR_LDO 3.2 ms VIO Power-On Reset Delay (VDD Supplied by Internal LDO) tPOR_VIO2 3 ms LDO Wake-Up Command Power-On Reset Delay tWAKEUP_SW 3 ms Hardware Reset Delay (Internal LDO Disabled) tWAKEUP_HW 3 ms 1 For all specifications, the relative voltages for the AVDD and REF inputs follow the operating conditions specified in the reference and power requirements sections of Table 1. 2 The acquisition time for single-cycle command mode depends on the sample rate and SCK frequency (see the Single-Cycle Command Mode section). |
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