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AD4696 Datasheet(PDF) 39 Page - Analog Devices

Part # AD4696
Description  16-Bit, 16-Channel, 500 kSPS/1 MSPS, Easy Drive Multiplexed SAR ADCs
PDF  96 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD4696 Datasheet(HTML) 39 Page - Analog Devices

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Data Sheet
AD4695/AD4696
Rev. 0 | Page 39 of 96
To enable single-cycle command mode, set the STD_SEQ_EN bit
to 0, set the NUM_SLOTS_AS field to 0x00, and set the
CYC_CTRL bit to 1 (see Table 13).
When single-cycle command mode is enabled, the configuration
settings for each channel are set with the corresponding
CONFIG_INn register. Therefore, all analog inputs can have
different channel configuration options, analog input high-Z
mode enable settings, and threshold detection enable settings.
Configure each CONFIG_INn register before entering
conversion mode and initiating conversions.
Oversampling is not supported when single-cycle command
mode is enabled. Set the OSR for all analog inputs to 1 before
entering conversion mode with single-cycle command mode
enabled (see the Oversampling and Decimation section).
CNV
CONV
ACQ
CONV
ACQ
CONV
ACQ
CONV
ACQ
ADC
PHASE
IN0
IN2
IN15
TEMP
IN0
MUX
CHANNEL
BUSY
IN0 RESULT
IN2 RESULT
IN15 RESULT
TEMP RESULT
SDOx
Figure 73. Standard Sequencer Example with OSR = 1
CNV
CONV
ACQ
CONV
ACQ
CONV
ACQ
CONV
ACQ
CONV
ACQ
ADC
PHASE
IN6
IN10
IN6
IN3
TEMP
IN6
MUX
CHANNEL
BUSY
IN6 RESULT
IN10 RESULT
IN6 RESULT
IN3 RESULT
TEMP RESULT
SDOx
Figure 74. Advanced Sequencer Example with OSR = 1 for All Channels
12
N-1
N
1
CNV
CONV
ACQ
CONV
ACQ
CONV
ACQ
CONV
ACQ
ADC
PHASE
IN0
IN1
MUX
CHANNEL
BUSY
IN0 RESULT
SDOx
Figure 75. Standard Sequencer and Advanced Sequencer SPI Frames with IN0 OSR = N
CNV
CONV
ACQ
CONV
ACQ
CONV
ACQ
CONV
ACQ
ADC
PHASE
IN13
IN9
IN8
TEMP
IN4
IN4
MUX
CHANNEL
BUSY
ON GPx
CMD = 0x18
CMD = 0x0F
CMD = 0x14
CMD = 0x14
CMD = 0x1A
SDI
IN13 RESULT
IN9 RESULT
IN8 RESULT
TEMP RESULT
IN4 RESULT
SDOx
Figure 76. Two-Cycle Command Mode Timing



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